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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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IMX7SCEC 데이터시트(PDF) 76 Page - NXP Semiconductors |
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IMX7SCEC 데이터시트(HTML) 76 Page - NXP Semiconductors |
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76 / 152 page  Electrical characteristics i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017 NXP Semiconductors 76 4.10.1.1 ECSPI Master mode timing Figure 44 depicts the timing of ECSPI in master mode. Table 52 lists the ECSPI master mode timing characteristics. Figure 44. ECSPI Master mode timing diagram Table 52. ECSPI Master mode timing parameters ID Parameter Symbol Min Max Unit CS1 ECSPIx_SCLK Cycle Time–Read ECSPIx_SCLK Cycle Time–Write tclk 43 15 —ns CS2 ECSPIx_SCLK High or Low Time–Read ECSPIx_SCLK High or Low Time–Write tSW 21.5 7 —ns CS3 ECSPIx_SCLK Rise or Fall1 1 See specific I/O AC parameters Section 4.6, “I/O AC parameters.” tRISE/FALL —— ns CS4 ECSPIx_SS_B pulse width tCSLH Half ECSPIx_SCLK period — ns CS5 ECSPIx_SS_B Lead Time (CS setup time) tSCS Half ECSPIx_SCLK period - 4 — ns CS6 ECSPIx_SS_B Lag Time (CS hold time) tHCS Half ECSPIx_SCLK period - 2 — ns CS7 ECSPIx_MOSI Propagation Delay (CLOAD =20 pF) tPDmosi -1 1 ns CS8 ECSPIx_MISO Setup Time tSmiso 18 — ns CS9 ECSPIx_MISO Hold Time tHmiso 0— ns CS10 RDY to ECSPIx_SS_B Time2 2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. tSDRY 5— ns CS7 CS2 CS2 CS4 CS6 CS5 CS8 CS9 ECSPIx_SCLK ECSPIx_SS_B ECSPIx_MOSI ECSPIx_MISO ECSPIx_RDY_B CS10 CS3 CS3 CS1 |
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