IMX7SCEC datasheet(96/152 Pages) NXP

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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

4.10.8.4

Possible

ΔVCMTX and ΔVOD Distortions of the Single-ended HS Signals

Figure 66. Possible

ΔVCMTX and ΔVOD Distortions of the Single-ended HS Signals

4.10.8.5

MIPI PHY switching characteristics

Table 70. Electrical and Timing Information

Symbol

Parameters

Test Conditions

Min

Typ

Max

Unit

HS Line Drivers AC Specifications

—

Maximum serial data rate (forward

direction)

On DATAP/N outputs.

Ω <= RL <= 125 Ω

—

1500

Mbps

FDDRCLK

DDR CLK frequency

On DATAP/N outputs.

—

750

MHz

PDDRCLK

DDR CLK period

Ω<= RL< = 125 Ω

1.33

—

tCDC

DDR CLK duty cycle

tCDC = tCPH / PDDRCLK

—50

—

tCPH

DDR CLK high time

—

tCPL

DDR CLK low time

—

DDR CLK / DATA Jitter

—

ps pk–pk

tSKEW[PN]

Intra-Pair (Pulse) skew

—

0.075

—

tSKEW[TX]

Data to Clock Skew

—

0.350

—

0.650

Differential output signal rise time

20% to 80%, RL = 50

150

—

0.3UI

Differential output signal fall time

20% to 80%, RL = 50

150

—

0.3UI

ΔVCMTX(HF)

Common level variation above 450 MHz 80

Ω<= RL< = 125 Ω

——

mVrms

ΔVCMTX(LF)

Common level variation between 50

MHz and 450 MHz.

Ω<= RL< = 125 Ω

——

mVp

VOD(0)

VOD(1)

VOD/2

VOD (SE H S Signals)

Static VCMTX (SE HS Signals)

Dynamic VCMTX (SE HS Signals)

VDN

VCM TX

VDP

VDN

VCMTX

VDP

VDN

VCM TX

VDP

VOD(0)

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