IMX7SCEC datasheet(65/152 Pages) NXP

65 / 152 page

Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

4.8.4.3

LPDDR2 parameters

Figure 30 shows the LPDDR2 basic timing diagram. The timing parameters for this diagram appear in

Table 46.

Figure 30. LPDDR2 command and address timing diagram

Table 46. LPDDR2 timing parameters1,2

1 All measurements are in reference to Vref level.

2 Measurements were done using balanced load and 25 Ω resistor from outputs to DDR_VREF

Parameter

Symbol

CK = 533 MHz

Unit

Min

Max

LP1

SDRAM clock high-level width

tCH

0.45

0.55

tCK

LP2

SDRAM clock low-level width

tCL

0.45

0.55

tCK

LP3

DRAM_CSx_B, DRAM_SDCKEx setup time

tIS

370

—

LP4

DRAM_CSx_B, DRAM_SDCKEx hold time

tIH

370

—

LP3

DRAM_CAS_B setup time

tIS

770

—

LP4

DRAM_CAS_B hold time

tIH

770

—

DRAM_SDCLKx_P

DRAM_CSx_B

DRAM_SDCKEx

DRAM_CAS_B

LP4

LP3

LP4

LP3

LP2

LP3

LP1

IMX7SCEC 데이터시트(PDF) 65 Page - NXP Semiconductors

IMX7SCEC 데이터시트(HTML) 65 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL