IMX7SCEC datasheet(87/152 Pages) NXP

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Electrical characteristics

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

4.10.3.3

Signal switching specifications

The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver

devices.

Table 63. RMII signal timing

Characteristic

Min.

Max.

Unit

M16

ENET_CLK pulse width high

35%

65%

ENET_CLK period

M17

ENET_CLK pulse width low

35%

65%

ENET_CLK period

M18

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid

—

M19

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid

—

M20

ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to

ENET_CLK setup

4—

M21

ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER

hold

2—

Table 64. RGMII signal switching specifications1

1 The timings assume the following configuration:

DDR_SEL = (11)b

DSE (drive-strength) = (111)b

Symbol

Description

Min.

Max.

Unit

Tcyc

2 For 10 Mbps and 100 Mbps, T

cyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.

Clock cycle duration

7.2

8.8

TskewT

3 For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an additional

trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value

is unspecified.

Data to clock output skew at transmitter

-500

500

TskewR

Data to clock input skew at receiver

2.6

Duty_G4

4 Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long

as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned

between.

Duty cycle for Gigabit

Duty_T4

Duty cycle for 10/100T

Tr/Tf

Rise/fall time (20–80%)

—

0.75

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