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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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W6100 데이터시트(PDF) 34 Page - WIZnet Co., Ltd |
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W6100 데이터시트(HTML) 34 Page - WIZnet Co., Ltd |
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34 / 149 page  W6100 – Hardwired Dual TCP/IP Stack Controller 34/149 4.1.12 IRCLR (IR Clear Register) [W1] [0x2108] [0x00] When the IRCLR bit corresponding to a specific bit of IR is written as '1', IR bit is cleared. 7 6 5 4 3 2 1 0 WOL UNR6 IPCONF UNR4 PTERM W1 W1 W1 W1 W1 4.1.13 SIMR (SOCKET Interrupt Mask Register) [R=W] [0x2114] [0x00] SIMR masks bit corresponding in SIR. 7 6 5 4 3 2 1 0 S7_INT S6_INT S5_INT S4_INT S3_INT S2_INT S1_INT S0_INT R=W R=W R=W R=W R=W R=W R=W R=W Bit Symbol Description [7:0] Sn_INT SOCKET n Interrupt Mask 1 : Enable SOCKET n Interrupt 0 : Disable SOCKET n Interrupt 4.1.14 SLIMR (SOCKET-less Interrupt Mask Register) [R=W] [0x2124] [0x00] SIMR masks bit corresponding in SLIR. 7 6 5 4 3 2 1 0 TOUT ARP4 PING4 ARP6 PING6 NS RS RA R=W R=W R=W R=W R=W R=W R=W R=W Bit Symbol Description 7 TOUT TIMEOUT Interrupt Mask 1 : Enable TIMEOUT Interrupt 0 : Disable TIMEOUT Interrupt 6 ARP4 ARP Interrupt Mask 1 : Enable ARP4 Interrupt 0 : Disable ARP4 Interrupt 5 PING4 PING Interrupt Mask 1 : Enable PING4 Interrupt |
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