W6100 datasheet(38/149 Pages) WIZNET

38 / 149 page

W6100 – Hardwired Dual TCP/IP Stack Controller

38/149

Bit

Symbol

Description

[7:5]

Reserved

[4:0]

ADDR

[4:0]

PHY Register Address

Set PHY Register Address

4.1.20 PHYDIR (PHY Data Input Register)

[R=W] [0x300C-0x300D] [0x0000]

PHYDIR sets the value to write into the PHY Register specified by PHYRAR.

Ex) PHYDIR = 0x1234

PHYDIR0(0x300C)

PHYDIR1(0x300D)

0x34

0x12

4.1.21 PHYDOR (PHY Data Output Register)

[RO] [0x3010-0x3011] [0x0000]

PHYDOR gets the value from the PHY Register specified by PHYRAR.

Ex) PHYDOR = 0x1234

PHYDOR0(0x0042)

PHYDPR1(0x0043)

0x34

0x12

4.1.22 PHYACR (PHY Access Control Register)

[RW, AC] [0x3014] [0x00]

PHYACR reads/writes the value in PHYDOR/PHYDIR from/to PHY register specified by

PHYRAR. After completion, PHYACR is automatically cleared.

Access Type

Value

related Register

Write

0x01

PHYDIR

Read

0x02

PHYDOR

4.1.23 PHYDIVR (PHY Division Register)

[R=W] [0x3018] [0x01]

PHYDIVR is PHY’s MDC Clock Division Register (be careful to not exceed 2.5MHz).

Value

Divider

SYS_CLK=100MHz

SYS_CLK=25MH

0x00

1/32

3.125MHz (N/A)

781.25KHz

0x01

1/64

1.5625MHz

390.625KHz

Others

1/128

781.25KHz

195.3125KHz

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