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VR4102 데이터시트(PDF) 133 Page - NEC

부품명 VR4102
상세설명  64/32-bit Microprocessor
PDF  701 Pages
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제조업체  NEC [NEC]
홈페이지  http://www.nec.com/
Logo NEC - NEC

VR4102 데이터시트(HTML) 133 Page - NEC

Back Button VR4102 Datasheet HTML 129Page - NEC VR4102 Datasheet HTML 130Page - NEC VR4102 Datasheet HTML 131Page - NEC VR4102 Datasheet HTML 132Page - NEC VR4102 Datasheet HTML 133Page - NEC VR4102 Datasheet HTML 134Page - NEC VR4102 Datasheet HTML 135Page - NEC VR4102 Datasheet HTML 136Page - NEC VR4102 Datasheet HTML 137Page - NEC Next Button
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CHAPTER 5 MEMORY MANAGEMENT SYSTEM
133
(8) xkphys (64-bit Kernel mode, physical spaces)
When the KX = 1 in the Status register and bits 63 and 62 of the virtual address space are 10, the virtual
address space is called xkphys and selected as either cached or uncached. If any of bits 58 to 32 of the
address is 1, an attempt to access that address results in an address error.
Whether cache can be used or not is determined by bits 59 to 61 of the virtual address. Table 5-5 shows
cacheability corresponding to 8 address spaces.
Table 5-5. Cacheability and the xkphys Address Space
Bits 61-59
Cacheability
Start address
0
Cached
0x8000 0000 0000 0000
to
0x8000 0000 FFFF FFFF
1
Cached
0x8800 0000 0000 0000
to
0x8800 0000 FFFF FFFF
2
Uncached
0x9000 0000 0000 0000
to
0x9000 0000 FFFF FFFF
3
Cached
0x9800 0000 0000 0000
to
0x9800 0000 FFFF FFFF
4
Cached
0xA000 0000 0000 0000
to
0xA000 0000 FFFF FFFF
5
Cached
0xA800 0000 0000 0000
to
0xA800 0000 FFFF FFFF
6
Cached
0xB000 0000 0000 0000
to
0xB000 0000 FFFF FFFF
7
Cached
0xB800 0000 0000 0000
to
0xB800 0000 FFFF FFFF
(9) xkseg (64-bit Kernel mode, physical spaces)
When the KX = 1 in the Status register and bits 63 and 62 of the virtual address space are 11, the virtual
address space is called xkseg and selected as either of the following:
• kernel virtual space, xkseg, the current kernel virtual space; the virtual address is extended with the contents
of the 8-bit ASID field to form a unique virtual address
References to xkseg are mapped through TLB. Whether cache can be used or not is determined by bit C of
each page’s TLB entry.
• one of the four 32-bit kernel compatibility spaces, as described in the next section.



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