VR4102 datasheet(146/701 Pages) NEC

146 / 701 page

CHAPTER 5 MEMORY MANAGEMENT SYSTEM

146

5.5 CP0 REGISTERS

The CP0 registers explained below are accessed by the memory management system and software.

parenthesized number that follows each register name is a register number.

5.5.1 Index Register (0)

The Index register is a 32-bit, read/write register containing five bits to index an entry in the TLB. The most-

significant bit of the register shows the success or failure of a TLB probe (TLBP) instruction.

The Index register also specifies the TLB entry affected by TLB read (TLBR) or TLB write index (TLBWI)

instructions.

Figure 5-12. Index Register

Index

: Indicates whether probing is successful or not. It is set to 1 if the latest TLBP instruction fails. It is

cleared to 0 when the TLBP instruction is successful.

Index : Specifies an index to a TLB entry that is a target of the TLBR or TLBWI instruction.

: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

5.5.2 Random Register (1)

The Random register is a read-only register. The low-order 5 bits are used in referencing a TLB entry. This

follows:

— The lower bound is the content of the Wired register.

— The upper bound is 31.

The Random register specifies the entry in the TLB that is affected by the TLBWR instruction. The register is

readable to verify proper operation of the processor.

The Random register is set to the value of the upper bound upon Cold Reset. This register is also set to the

upper bound when the Wired register is written. Figure 5-13 shows the format of the Random register.

Figure 5-13. Random Register

Random

Random : TLB random index

: Reserved for future use. Write 0 in a write operation. When this field is read, 0 is read.

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