IMX6SDLCEC datasheet(105/169 Pages) NXP

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Electrical Characteristics

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018

NXP Semiconductors

105

4.11.11 LVDS Display Bridge (LDB) Module Parameters

The LVDS interface complies with TIA/EIA 644-A standard. For more details, see TIA/EIA STANDARD

644-A, “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”.

4.11.12 MIPI D-PHY Timing Parameters

This section describes MIPI D-PHY electrical specifications, compliant with MIPI CSI-2 version 1.0,

D-PHY specification Rev. 1.0 (for MIPI sensor port x2 lanes) and MIPI DSI Version 1.01, and D-PHY

specification Rev. 1.0 (and also DPI version 2.0, DBI version 2.0, DSC version 1.0a at protocol layer) (for

MIPI display port x2 lanes).

4.11.12.1 Electrical and Timing Information

Table 69. LVDS Display Bridge (LDB) Electrical Specification

Parameter

Symbol

Test Condition

Min

Max

Units

Differential Voltage Output Voltage

VOD

100

Ω Differential load

250

450

Output Voltage High

Voh

100

Ω differential load (0 V Diff—Output High

Voltage static)

1.25

1.6

Output Voltage Low

Vol

100

Ω differential load (0 V Diff—Output Low

Voltage static)

0.9

1.25

Offset Static Voltage

VOS

Two 49.9

Ω resistors in series between N-P

terminal, with output in either Zero or One state, the

voltage measured between the 2 resistors.

1.15

1.375

VOS Differential

VOSDIFF Difference in VOS between a One and a Zero state

-50

Output short circuited to GND

ISA ISB

With the output common shorted to GND

-24

VT Full Load Test

VTLoad

100

Ω Differential load with a 3.74 kΩ load between

GND and IO Supply Voltage

247

454

Table 70. Electrical and Timing Information

Symbol

Parameters

Test Conditions

Min

Typ

Max

Unit

Input DC Specifications - Apply to DSI_CLK_P/DSI_CLK_N and DSI_DATA_P/DSI_DATA_N inputs

Input signal voltage range

Transient voltage range is

limited from -300 mV to

1600 mV

-50

—

1350

VLEAK

Input leakage current

VGNDSH(min) = VI =

VGNDSH(max) +

VOH(absmax)

Lane module in LP Receive

Mode

-10

—

VGNDSH

Ground Shift

—

-50

—

VOH(absmax)

Maximum transient output

voltage level

——

—

1.45

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