 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
IMX6SDLCEC 데이터시트(PDF) 107 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
IMX6SDLCEC 데이터시트(HTML) 107 Page - NXP Semiconductors |
|
|
107 / 169 page  Electrical Characteristics i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 NXP Semiconductors 107 4.11.12.2 MIPI D-PHY Signaling Levels The signal levels are different for differential HS mode and single-ended LP mode. Figure 67 shows both the HS and LP signal levels on the left and right sides, respectively. The HS signaling levels are below the LP low-level input threshold such that LP receiver always detects low on HS signals. Figure 67. D-PHY Signaling Levels ZID Differential input impedance — 80 — 125 Ω LP Line Receiver DC Specifications VIL Input low voltage — — — 550 mV VIH Input high voltage — 920 — — mV VHYST Input hysteresis — 25 — — mV Contention Line Receiver DC Specifications VILF Input low fault threshold — 200 — 450 mV Table 70. Electrical and Timing Information (continued) Symbol Parameters Test Conditions Min Typ Max Unit HS Vout Range HS Vcm Range Max VOD Min VOD VCMTX,MIN VOLHS VCMTX,MAX VOHHS LP VIL LP VOL LP VIH VOH,MAX VOH,MIN VIH VIL LP Threshold Region VGNDSH,MA X VGNDSH,MIN GND LP VOL HS Differential Signaling LP Single-ended Signaling |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
