HCS08 datasheet(280/316 Pages) NXP

280 / 316 page

MC9S08SG8 MCU Series Data Sheet, Rev. 8

280

Freescale Semiconductor

17.4.3.7

Debug Control Register (DBGC)

This register can be read or written at any time.

654

321

DBGEN

ARM

TAG

BRKEN

RWA

RWAEN

RWB

RWBEN

Reset

000

Figure 17-7. Debug Control Register (DBGC)

Table 17-4. DBGC Register Field Descriptions

Field

Description

DBGEN

Debug Module Enable — Used to enable the debug module. DBGEN cannot be set to 1 if the MCU is secure.

0DBG disabled

1 DBG enabled

ARM

Arm Control — Controls whether the debugger is comparing and storing information in the FIFO. A write is used

to set this bit (and ARMF) and completion of a debug run automatically clears it. Any debug run can be manually

stopped by writing 0 to ARM or to DBGEN.

0 Debugger not armed

1 Debugger armed

TAG

Tag/Force Select — Controls whether break requests to the CPU will be tag or force type requests. If

BRKEN = 0, this bit has no meaning or effect.

0 CPU breaks requested as force type requests

1 CPU breaks requested as tag type requests

BRKEN

Break Enable — Controls whether a trigger event will generate a break request to the CPU. Trigger events can

cause information to be stored in the FIFO without generating a break request to the CPU. For an end trace, CPU

break requests are issued to the CPU when the comparator(s) and R/W meet the trigger requirements. For a

begin trace, CPU break requests are issued when the FIFO becomes full. TRGSEL does not affect the timing of

CPU break requests.

0 CPU break requests not enabled

1 Triggers cause a break request to the CPU

RWA

R/W Comparison Value for Comparator A — When RWAEN = 1, this bit determines whether a read or a write

access qualifies comparator A. When RWAEN = 0, RWA and the R/W signal do not affect comparator A.

0 Comparator A can only match on a write cycle

1 Comparator A can only match on a read cycle

RWAEN

Enable R/W for Comparator A — Controls whether the level of R/W is considered for a comparator A match.

0 R/W is not used in comparison A

1 R/W is used in comparison A

RWB

R/W Comparison Value for Comparator B — When RWBEN = 1, this bit determines whether a read or a write

access qualifies comparator B. When RWBEN = 0, RWB and the R/W signal do not affect comparator B.

0 Comparator B can match only on a write cycle

1 Comparator B can match only on a read cycle

RWBEN

Enable R/W for Comparator B — Controls whether the level of R/W is considered for a comparator B match.

0 R/W is not used in comparison B

1 R/W is used in comparison B

HCS08 데이터시트(PDF) 280 Page - NXP Semiconductors

HCS08 데이터시트(HTML) 280 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL