HCS08 datasheet(281/316 Pages) NXP

281 / 316 page

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor

281

17.4.3.8

Debug Trigger Register (DBGT)

This register can be read any time, but may be written only if ARM = 0, except bits 4 and 5 are hard-wired

to 0s.

654

321

TRGSEL

BEGIN

TRG3

TRG2

TRG1

TRG0

Reset

000

= Unimplemented or Reserved

Figure 17-8. Debug Trigger Register (DBGT)

Table 17-5. DBGT Register Field Descriptions

Field

Description

TRGSEL

Trigger Type — Controls whether the match outputs from comparators A and B are qualified with the opcode

tracking logic in the debug module. If TRGSEL is set, a match signal from comparator A or B must propagate

through the opcode tracking logic and a trigger event is only signalled to the FIFO logic if the opcode at the match

address is actually executed.

0 Trigger on access to compare address (force)

1 Trigger if opcode at compare address is executed (tag)

BEGIN

Begin/End Trigger Select — Controls whether the FIFO starts filling at a trigger or fills in a circular manner until

a trigger ends the capture of information. In event-only trigger modes, this bit is ignored and all debug runs are

assumed to be begin traces.

0 Data stored in FIFO until trigger (end trace)

1 Trigger initiates data storage (begin trace)

3:0

TRG[3:0]

Select Trigger Mode — Selects one of nine triggering modes, as described below.

0000 A-only

0001 A OR B

0010 A Then B

0011 Event-only B (store data)

0100 A then event-only B (store data)

0101 A AND B data (full mode)

0110 A AND NOT B data (full mode)

0111 Inside range: A

 address  B

1000 Outside range: address < A or address > B

1001 – 1111 (No trigger)

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