ST72324BJ2 datasheet(147/188 Pages) STMICROELECTRONICS

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ST72324B

Electrical characteristics

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12.6.4

RC oscillators

Figure 68.

Typical fOSC(RCINT) vs TA

Note:

To reduce disturbance to the RC oscillator, it is recommended to place decoupling

capacitors between VDD and VSS as shown in Figure 87 on page 165.

12.6.5

PLL characteristics

The user must take the PLL jitter into account in the application (for example in serial

communication or sampling of high frequency signals). The PLL jitter is a periodic effect,

Table 96.

OSCRANGE selection for typical resonators

Supplier

fOSC

(MHz)

Typical ceramic resonators(1)

Resonator characteristics given by the ceramic resonator manufacturer.

Reference

Recommended OSCRANGE

option bit configuration

Murata

CSTCC2M00G56A-R0

MP mode(2)

LP mode is not recommended for 2 MHz resonator because the peak to peak amplitude is too small

(>0.8V). For more information on these resonators, please consult www.murata.com.

CSTCR4M00G55B-R0

MS mode

CSTCE8M00G52A-R0

HS mode

CSTCE16M0V51A-R0

HS mode

Table 97.

RC oscillators

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fOSC (RCINT)

Internal RC oscillator frequency

(see Figure 68)

TA =25°C, VDD =5V

3.5

5.6

MHz

3.2

3.4

3.6

3.8

-45

130

TA(°C)

Vdd= 5V

Vdd= 5.5V

Table 98.

PLL characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fOSC

PLL input frequency range

MHz

∆ fCPU/fCPU Instantaneous PLL jitter(1)

Data characterized but not tested

fOSC = 4 MHz

0.7

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