ST72324BJ2 datasheet(148/188 Pages) STMICROELECTRONICS

148 / 188 page

Electrical characteristics

ST72324B

148/188

which is integrated over several CPU cycles. Therefore the longer the period of the

application signal, the less it will be impacted by the PLL jitter.

Figure 69 shows the PLL jitter integrated on application signals in the range 125 kHz to

2 MHz. At frequencies of less than 125 kHz, the jitter is negligible.

Figure 69.

Integrated PLL jitter vs signal frequency(1)

Measurement conditions: fCPU = 8 MHz

12.7

Memory characteristics

12.7.1

RAM and hardware registers

12.7.2

Flash memory

0.2

0.4

0.6

0.8

1.2

4 MHz

2 MHz

1 MHz 500 kHz 250 kHz 125 kHz

Application Frequency

+/-Jitter (%)

Max

Typ

Table 99.

RAM and hardware registers

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VRM

Data retention mode(1)

Minimum VDD supply voltage without losing data stored in RAM (in Halt mode or under reset) or in

hardware registers (only in Halt mode). Not tested in production.

Halt mode (or reset)

1.6

Table 100.

Dual voltage HDFlash memory

Symbol

Parameter

Conditions

Min(1)

Typ

Max(1)

Unit

fCPU

Operating frequency

Read mode

MHz

Write/Erase mode

VPP

Programming voltage(2)

4.5V < VDD < 5.5V

11.4

12.6

IDD

Supply current(3)

Write/Erase

<10

µA

IPP

VPP current

(3)

Read (VPP = 12V)

200

µA

Write/Erase

tVPP

Internal VPP stabilization time

µs

tRET

Data retention

TA=85°C

years

TA=105°C

TA=125°C

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