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TMP93CS32F 데이터시트(PDF) 140 Page - Toshiba Semiconductor

부품명 TMP93CS32F
상세설명  CMOS 16-Bit Microcontroller
PDF  180 Pages
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
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TMP93CS32F 데이터시트(HTML) 140 Page - Toshiba Semiconductor

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TMP93CS32
2004-02-10
93CS32-138
3.10.2
Operation
(1) Analog reference voltage
High analog reference voltage is applied to the VREFH pin, and low analog reference
voltage is applied to the VREFL pin. The voltage between VREFH and VREFL is
divided into 1024 increments using a string resistor. AD conversion is based on
comparing the analog input voltage with these reference voltage increments.
To turn the switch between VREFH and VREFL off, program “0” to the
ADMOD1<VREFON> bit.
To start AD conversion when the switch is off, first program “1” to <VREFON>. After
that, wait at 3
µs long enough to get the stabilized oscillation, program “1” to
ADMOD0<ADS>.
(2) Selecting analog input channels
The procedure for selecting analog input channels depends on the operating mode of
the AD converter.
•
When analog input channel is used to fix (ADMOD0<SCAN>
= “0”)
To set ADMOD1<ADCH2:0>, selecting one channel from analog input pins AN0
to AN5.
•
When analog input channel is used to scan (ADMOD0<SCAN>
= “1”)
To set ADMOD1<ADCH2:0>, selecting one channel from 6 scan mode.
Table 3.10.1 shows the analog input channel selection each operating mode.
A reset initializes AD mode control register ADMOD1<ADCH2:0> to “000”,
selecting pin AN0 for the AD converter input.
The pins not used as analog input channels can be used as general-purpose input
ports (P5).
Table 3.10.1 Analog Input Channel Selection
<ADCH2:0>
Fixed Channel
<SCAN>
= 0
Channel Scan
<SCAN>
= 1
000
AN0
AN0
001
AN1
AN0
→ AN1
010
AN2
AN0
→ AN1 → AN2
011
AN3
AN0
→ AN1 → AN2 → AN3
100
AN4
AN4
101
AN5
AN4
→ AN5
110
111
Don’t care
(3) Starting AD conversion
AD conversion starts when ADMOD0<ADS> to “1”, or ADMOD1<ADTRGE> is set to
“1” and the falling edge is input through ADTRG pin.
When AD conversion starts, AD conversion busy flag ADMOD0<ADBF> is set to “1”,
indicating AD conversion is in progress.
Writing “1” to <ADS> while conversion is in progress restarts the conversion. Check
the conversion result stored flag ADREGxL<ADRxRF> to determine whether the AD
conversion data are valid at this time.
Inputting the falling edge to the ADTRG pin while conversion is in progress is
invalid.



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