| 전자부품 데이터시트 검색엔진 |
|
TMP93CS32F 데이터시트(PDF) 142 Page - Toshiba Semiconductor |
|
|
|||||||||||||||||||||||||||||
TMP93CS32F 데이터시트(HTML) 142 Page - Toshiba Semiconductor |
|
142 / 180 page ![]() TMP93CS32 2004-02-10 93CS32-140 Table 3.10.2shows the relations between AD conversion modes and interrupt request. Table 3.10.2 Relation between AD Conversion Modes and Interrupt Request ADMOD0 Mode Interrupt Request Timing <ITM0> <REPET> <SCAN> Fixed channel single conversion mode After conversion X 0 0 Channel scan single conversion mode After conversion X 0 1 Fixed channel repeat conversion mode (Every conversion) After every conversion 0 Fixed channel repeat conversion mode (Every fourth conversion) After every fourth conversion 1 1 0 Channel scan repeat conversion mode After every scan conversion X 1 1 X: Don’t care (5) AD conversion time 140 states (14 µs at fc = 20 MHz) are required for AD conversion of one channel. (6) Storing and reading the AD conversion result AD conversion results are stored in AD conversion result registers high/low (ADREG04H/L to ADREG3H/L). These registers are read only. In fixed channel repeat conversion mode, AD conversion results are stored in order from ADREG04H/L to ADREG3H/L. Except in this mode, AD conversion results for channel AN0 and AN4, AN1 and AN5, AN2, AN3 are stored severally ADREG04H/L, ADREG15H/L, ADREG2H/L, ADREG3H/L. Table 3.10.3 shows correspondence between analog input channels and AD conversion result registers. Table 3.10.3 Correspondence Between Analog Input Channels and AD Conversion Result Registers AD Conversion Result Registers Analog Input Channel (port 5) Conversion Modes Except Right Fixed Channel Repeat Conversion Mode (Every fourth conversion) AN0 ADREG04H/L AN1 ADREG15H/L AN2 ADREG2H/L AN3 ADREG3H/L AN4 ADREG04H/L AN5 ADREG15H/L ADREG04H/L ADREG15H/L ADREG2H/L ADREG3H/L AD conversion result registers bit0 is AD conversion result stored flag <ADRxRF>. The flag shows that whether those registers are read or not. When AD conversion results are stored in those registers (ADREGxH or ADREGxL), this flag is set to “1”. When each register is read, this flag is cleared to “0”, and AD conversion end flag ADMOD0<EOCF> is also cleared to “0”. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |