TMP93CS32F datasheet(145/180 Pages) TOSHIBA

145 / 180 page

TMP93CS32

2004-02-10

93CS32-143

The watchdog timer consists of 7-stage and 15-stage binary counters which use System

clock (fSYS) as the input clock. The 15-stage binary counter has fSYS/215, fSYS/217, fSYS/219,

and fSYS/221 output. Selecting one of the outputs with the WDMOD<WDTP1:0> register

generates a watchdog interrupt when an overflow occurs. The binary counter for the

watchdog timer should be cleared to “0” with runaway detecting result software

(instruction) before an interrupt occurs.

Example:

LDW

(WDMOD), B100H

;

Disable.

(WDCR), 4EH

;

Write clear code.

SET

7, (WDMOD)

;

Enable again.

The runaway detecting result can also be connected to the reset pin internally. In this

case, the watchdog timer resets itself.

Figure 3.11.2 Normal Mode

Figure 3.11.3 Reset Mode

For warm-up counter, 27 and 29 output of 15-stage binary counter can be selected using

WDMOD<WARM> register. When a stable-external oscillator is used, shorter warm-up

time is available using T45CR<QCU> register. When <QCU>

= 1, counting value 27 is

selected.

When the watchdog timer is in operation, this shorter warm-up time function cannot be

available. This function can be available by setting <QCU>

= 0.

Overflow

WDT counter

WDT interrupt

WDT clear

(Soft ware)

Write clear code

WDT counter

WDT interrupt

8 to 20 states (12.8 to 32

µs at 20 MHz)

Overflow

Internal reset

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