HCS08 datasheet(159/198 Pages) NXP

159 / 198 page

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

159

Chapter 12

Development Support

12.1

Introduction

Development support systems in the HCS08 include the background debug controller (BDC). The BDC

provides a single-wire debug interface to the target MCU that provides a convenient interface for

programming the on-chip flash and other nonvolatile memories. The BDC is also the primary debug

interface for development and allows non-intrusive access to memory data and traditional debug features

such as CPU register modify, breakpoints, and single instruction trace commands.

In the HCS08 Family, address and data bus signals are not available on external pins (not even in test

modes). Debug is done through commands fed into the target MCU via the single-wire background debug

interface. The debug module provides a means to selectively trigger and capture bus information so an

external development system can reconstruct what happened inside the MCU on a cycle-by-cycle basis

without having external access to the address and data signals.

12.1.1

Forcing Active Background

The method for forcing active background mode depends on the specific HCS08 derivative. For the

MC9S08QD4 series, you can force active background mode by holding the BKGD pin low as the MCU

exits the reset condition independent of what caused the reset. If no debug pod is connected to the BKGD

pin, the MCU will always reset into normal operating mode.

12.1.2

Module Configuration

The alternative BDC clock source for MC9S08QD4 series is the ICGCLK. See Chapter 9, “Internal Clock

Source (S08ICSV1),” for more information about ICGCLK and how to select clock sources.

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