HCS08 datasheet(37/198 Pages) NXP

37 / 198 page

Chapter 4 Memory Map and Register Definition

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

For compatibility with M68HC05 MCUs, the HCS08 resets the stack pointer to 0x00FF. In the

MC9S08QD4 series, it is usually best to reinitialize the stack pointer to the top of the RAM so the direct

page RAM can be used for frequently accessed RAM variables and bit-addressable program variables.

Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated

to the highest address of the RAM in the Freescale Semiconductor-provided equate file).

LDHX

#RamLast+1

;point one past RAM

TXS

;SP<-(H:X-1)

When security is enabled, the RAM is considered a secure memory resource and is not accessible through

BDM or through code executing from non-secure memory. See Section 4.6, “Security,” for a detailed

description of the security feature.

4.5

Flash

The flash memory is intended primarily for program storage. In-circuit programming allows the operating

program to be loaded into the flash memory after final assembly of the application product. It is possible

to program the entire array through the single-wire background debug interface. Because no special

voltages are needed for flash erase and programming operations, in-application programming is also

possible through other software-controlled communication paths. For a more detailed discussion of

in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I,

Freescale Semiconductor document order number HCS08RMv1.

4.5.1

Features

Features of the flash memory include:

•

Flash size

— MC9S08QD4/S9S08QD4: 4096 bytes (8 pages of 512 bytes each)

— MC9S08QD2/S9S08QD2: 2048 bytes (4 pages of 512 bytes each)

•

Single power supply program and erase

•

Command interface for fast program and erase operation

•

Up to 100,000 program/erase cycles at typical voltage and temperature

•

Flexible block protection

•

Security feature for flash and RAM

•

Auto power-down for low-frequency read accesses

4.5.2

Program and Erase Times

Before any program or erase command can be accepted, the flash clock divider register (FCDIV) must be

written to set the internal clock for the flash module to a frequency (fFCLK) between 150 kHz and 200 kHz

(see Section 4.7.1, “Flash Clock Divider Register (FCDIV).”) This register can be written only once, so

normally this write is performed during reset initialization. FCDIV cannot be written if the access error

flag, FACCERR in FSTAT, is set. The user must ensure that FACCERR is not set before writing to the

FCDIV register. One period of the resulting clock (1/fFCLK) is used by the command processor to time

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