HCS08 datasheet(51/198 Pages) NXP

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MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

Chapter 5

Resets, Interrupts, and General System Control

5.1

Introduction

This chapter discusses basic reset and interrupt mechanisms and the various sources of reset and interrupts

in the MC9S08QD4 series. Some interrupt sources from peripheral modules are discussed in greater detail

within other sections of this data sheet. This section gathers basic information about all reset and interrupt

sources in one place for easy reference. A few reset and interrupt sources, including the computer

operating properly (COP) watchdog and real-time interrupt (RTI), are not part of on-chip peripheral

systems with their own chapters but are part of the system control logic.

5.2

Features

Reset and interrupt features include:

•

Multiple sources of reset for flexible system configuration and reliable operation

•

Reset status register (SRS) to indicate source of most recent reset

•

Separate interrupt vectors for each module (reduces polling overhead) (see Table 5-2)

5.3

MCU Reset

Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,

most control and status registers are forced to initial values and the program counter is loaded from the

reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially

configured as general-purpose high-impedance inputs with pullup devices disabled. The I bit in the

condition code register (CCR) is set to block maskable interrupts so the user program has a chance to

initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset.

The MC9S08QD4 series has the following sources for reset:

•

External pin reset (PIN) - enabled using RSTPE in SOPT1

•

Power-on reset (POR)

•

Low-voltage detect (LVD)

•

Computer operating properly (COP) timer

•

Illegal opcode detect (ILOP)

•

Illegal address detect (ILAD)

•

Background debug forced reset

Each of these sources, with the exception of the background debug forced reset, has an associated bit in

the system reset status register.

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