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HCS08 데이터시트(PDF) 64 Page - NXP Semiconductors |
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HCS08 데이터시트(HTML) 64 Page - NXP Semiconductors |
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64 / 198 page ![]() Chapter 5 Resets, Interrupts, and General System Control MC9S08QD4 Series MCU Data Sheet, Rev. 6 64 Freescale Semiconductor 5.8.8 System Power Management Status and Control 1 Register (SPMSC1) This high-page register contains status and control bits to support the low voltage detect function, and to enable the bandgap voltage reference for use by the ADC module. To configure the low voltage detect trip voltage, see Table 5-13 for the LVDV bit description in SPMSC2. Table 5-11. Real-Time Interrupt Period RTIS2:RTIS1:RTIS0 Using Internal 1 kHz Clock Source1 2 1 Values are shown in this column based on t RTI =1ms. See tRTI in the Section A.8.1, “Control Timing,” for the tolerance of this value. 2 The initial RTI timeout period will be up to one 1 kHz clock period less than the time specified. Using 32 kHz ICS Clock Source Period = text 3 3 t ext is the period of the 32 kHz ICS frequency. 0:0:0 Disable RTI Disable RTI 0:0:1 8 ms text × 256 0:1:0 32 ms text × 1024 0:1:1 64 ms text × 2048 1:0:0 128 ms text × 4096 1:0:1 256 ms text × 8192 1:1:0 512 ms text × 16384 1:1:1 1.024 s text × 32768 76 54 32 1 1 0 RLVDF 0 LVDIE LVDRE2 LVDSE LVDE 2 0 BGBE W LVDACK Reset: 000 11 100 = Unimplemented or Reserved 1 Bit 1 is a reserved bit that must always be written to 0. 2 This bit can be written only one time after reset. Additional writes are ignored. Figure 5-10. System Power Management Status and Control 1 Register (SPMSC1) Table 5-12. SPMSC1 Register Field Descriptions Field Description 7 LVDF Low-Voltage Detect Flag — Provided LVDE = 1, this read-only status bit indicates a low-voltage detect event. 6 LVDACK Low-Voltage Detect Acknowledge — This write-only bit is used to acknowledge low voltage detection errors (write 1 to clear LVDF). Reads always return 0. |
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