HCS08 datasheet(65/198 Pages) NXP

65 / 198 page

Chapter 5 Resets, Interrupts, and General System Control

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

5.8.9

System Power Management Status and Control 2 Register

(SPMSC2)

This high-page register contains status and control bits to configure the stop mode behavior of the MCU.

See Section 3.6, “Stop Modes,” for more information on stop modes.

Figure 5-11. System Power Management Status and Control 2 Register (SPMSC2)

LVDIE

Low-Voltage Detect Interrupt Enable — This bit enables hardware interrupt requests for LVDF.

0 Hardware interrupt disabled (use polling).

1 Request a hardware interrupt when LVDF = 1.

LVDRE

Low-Voltage Detect Reset Enable — This write-once bit enables LVDF events to generate a hardware reset

(provided LVDE = 1).

0 LVDF does not generate hardware resets.

1 Force an MCU reset when LVDF = 1.

LVDSE

Low-Voltage Detect Stop Enable — Provided LVDE = 1, this read/write bit determines whether the low-voltage

detect function operates when the MCU is in stop mode.

0 Low-voltage detect disabled during stop mode.

1 Low-voltage detect enabled during stop mode.

LVDE

Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation

of other bits in this register.

0 LVD logic disabled.

1 LVD logic enabled.

BGBE

Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the

ADC module on one of its internal channels.

0 Bandgap buffer disabled.

1 Bandgap buffer enabled.

321

RLVWF

LVDV

LVWV

PPDF

PPDC1

1 This bit can be written only one time after reset. Additional writes are ignored.

LVWACK

PPDACK

POR:

2 LVWF will be set in the case when V

supply transitions below the trip point or after reset and Vsupply is already below VLVW.

000

LVDR:

000

Other

Reset

000

= Unimplemented or Reserved

U = Unaffected by reset

Table 5-12. SPMSC1 Register Field Descriptions (continued)

Field

Description

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