HCS08 datasheet(100/198 Pages) NXP

100 / 198 page

Analog-to-Digital Converter (S08ADC10V1)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

100

Freescale Semiconductor

RCOCO

AIEN

ADCO

ADCH

Reset:

= Unimplemented or Reserved

Figure 8-3. Status and Control Register (ADCSC1)

Table 8-3. ADCSC1 Register Field Descriptions

Field

Description

COCO

Conversion Complete Flag — The COCO flag is a read-only bit which is set each time a conversion is

completed when the compare function is disabled (ACFE = 0). When the compare function is enabled (ACFE =

1) the COCO flag is set upon completion of a conversion only if the compare result is true. This bit is cleared

whenever ADCSC1 is written or whenever ADCRL is read.

0 Conversion not completed

1 Conversion completed

AIEN

Interrupt Enable — AIEN is used to enable conversion complete interrupts. When COCO becomes set while

AIEN is high, an interrupt is asserted.

0 Conversion complete interrupt disabled

1 Conversion complete interrupt enabled

ADCO

Continuous Conversion Enable — ADCO is used to enable continuous conversions.

0 One conversion following a write to the ADCSC1 when software triggered operation is selected, or one

conversion following assertion of ADHWT when hardware triggered operation is selected.

1 Continuous conversions initiated following a write to ADCSC1 when software triggered operation is selected.

Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected.

4:0

ADCH

Input Channel Select — The ADCH bits form a 5-bit field which is used to select one of the input channels. The

input channels are detailed in Figure 8-4.

The successive approximation converter subsystem is turned off when the channel select bits are all set to 1.

This feature allows for explicit disabling of the ADC and isolation of the input channel from all sources.

Terminating continuous conversions this way will prevent an additional, single conversion from being performed.

It is not necessary to set the channel select bits to all 1s to place the ADC in a low-power state when continuous

conversions are not enabled because the module automatically enters a low-power state when a conversion

completes.

Figure 8-4. Input Channel Select

ADCH

Input Select

ADCH

Input Select

00000

AD0

10000

AD16

00001

AD1

10001

AD17

00010

AD2

10010

AD18

00011

AD3

10011

AD19

00100

AD4

10100

AD20

00101

AD5

10101

AD21

00110

AD6

10110

AD22

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