HCS08 datasheet(111/198 Pages) NXP

111 / 198 page

Analog-to-Digital Converter (S08ADC10V1)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

111

result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion

algorithm.

If the bus frequency is less than the fADCK frequency, precise sample time for continuous conversions

cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th

of the fADCK frequency, precise sample time for continuous conversions cannot be guaranteed when long

sample is enabled (ADLSMP=1).

The maximum total conversion time for different conditions is summarized in Table 8-12.

The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.

The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For

example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1

ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:

NOTE

The ADCK frequency must be between fADCK minimum and fADCK

maximum to meet ADC specifications.

Table 8-12. Total Conversion Time vs. Control Conditions

Conversion Type

ADICLK

ADLSMP

Max Total Conversion Time

Single or first continuous 8-bit

0x, 10

20 ADCK cycles + 5 bus clock cycles

Single or first continuous 10-bit

0x, 10

23 ADCK cycles + 5 bus clock cycles

Single or first continuous 8-bit

0x, 10

40 ADCK cycles + 5 bus clock cycles

Single or first continuous 10-bit

0x, 10

43 ADCK cycles + 5 bus clock cycles

Single or first continuous 8-bit

μs + 20 ADCK + 5 bus clock cycles

Single or first continuous 10-bit

μs + 23 ADCK + 5 bus clock cycles

Single or first continuous 8-bit

μs + 40 ADCK + 5 bus clock cycles

Single or first continuous 10-bit

μs + 43 ADCK + 5 bus clock cycles

Subsequent continuous 8-bit;

fBUS > fADCK

17 ADCK cycles

Subsequent continuous 10-bit;

fBUS > fADCK

20 ADCK cycles

Subsequent continuous 8-bit;

fBUS > fADCK/11

37 ADCK cycles

Subsequent continuous 10-bit;

fBUS > fADCK/11

40 ADCK cycles

23 ADCK cyc

Conversion time =

8 MHz/1

Number of bus cycles = 3.5

μs x 8 MHz = 28 cycles

5 bus cyc

8 MHz

= 3.5

μs

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