HCS08 datasheet(131/198 Pages) NXP

131 / 198 page

Internal Clock Source (S08ICSV1)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

131

9.4.4

Low Power Bit Usage

The low power bit (LP) is provided to allow the FLL to be disabled and thus conserve power when it is

not being used. However, in some applications it may be desirable to enable the FLL and allow it to lock

for maximum accuracy before switching to an FLL engaged mode. Do this by writing the LP bit to 0.

9.4.5

Internal Reference Clock

When IRCLKEN is set the internal reference clock signal will be presented as ICSIRCLK, which can be

used as an additional clock source. The ICSIRCLK frequency can be re-targeted by trimming the period

of the internal reference clock. This can be done by writing a new value to the TRIM bits in the ICSTRM

the ICSTRM register will speed up the ICSIRCLK frequency. The TRIM bits will effect the ICSOUT

frequency if the ICS is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or FLL bypassed

internal low power (FBILP) mode. The TRIM and FTRIM value will not be affected by a reset.

Until ICSIRCLK is trimmed, programming low reference divider (RDIV) factors may result in ICSOUT

frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing

specifications (see the Device Overview chapter).

If IREFSTEN is set and the IRCLKEN bit is written to 1, the internal reference clock will keep running

during stop mode in order to provide a fast recovery upon exiting stop.

All MCU devices are factory programmed with a trim value in a reserved memory location. This value can

be copied to the ICSTRM register during reset initialization. The factory trim value does not include the

FTRIM bit. For finer precision, the user can trim the internal oscillator in the application and set the

FTRIM bit accordingly.

9.4.6

Optional External Reference Clock

The ICS module can support an external reference clock with frequencies between 31.25 kHz to 5 MHz

in all modes. When the ERCLKEN is set, the external reference clock signal will be presented as

ICSERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference

clock will not be used by the FLL and will only be used as ICSERCLK. In these modes, the frequency can

be equal to the maximum frequency the chip-level timing specifications will support (see the Device

Overview chapter).

If EREFSTEN is set and the ERCLKEN bit is written to 1, the external reference clock will keep running

during stop mode in order to provide a fast recovery upon exiting stop.

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