AT90SCR100 datasheet(287/433 Pages) ATMEL

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287

TPR0327AY–SMS–30Jan09

AT90SCR100

21.5

HSSPI Interface Registers

21.5.1

HSSPICFG - HSSPI Config Register

• Bits 7..5 - SPICKDIV2..0: SPI Clock Divider Ratio Bits

Defines the HSSPI Clock divider ratio.

The following table gives, for each combination of SPICKDIV2, SPICKDIV1 and SPICKDIV0, the

division applied to the clock. Figure 7-1 on page 31 gives information about the clock tree and

base frequency for HSSPI.

Note:

1. Base frequency is clkIO = 96Mhz

• Bit 4 - DPRAM: DPRAM Bit

When set (one), this bit enables the DPRAM/HSSPIDMA systems.

When cleared (zero), this bit disables the DPRAM/HSSPIDMA systems.

• Bit 3 - HSCPHA: High Speed Clock PHAse Bit

The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or

trailing (last) edge of HSSCK. Refer to Figure 21-9 and Figure 21-10.

Bit

$0000D9

SPICKDIV [2..0]

DPRAM

HSCPHA HSCPOL

HSMSTR

HSSPIEN

HSSPICFG

Read/write

R/W

Initial value

0x80

Table 21-2.

HSSPI dividers(1)

SPICKDIV2

SCKCKDIV1

SCKCKDIV0

Divider

External clock divider ratio(1)

24 Mhz

19.2 Mhz

16 Mhz

12 Mhz

8 Mhz

4 Mhz

2 Mhz

1 Mhz

Any attempt at modifying the HSSPICFG.SPICKDIV value once the HSSPI Con-

troller is enabled will not affect the HSSPI Clock frequency.

After a DPRAM is disabled, the DPRAM is reset. This reset is active for two clock

cycles of the DPRAM clock. It is recommended to do nothing on the DPRAM dur-

ing these two clock cycles.

Note

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