AT90SCR100 datasheet(285/433 Pages) ATMEL

285 / 433 page

285

TPR0327AY–SMS–30Jan09

AT90SCR100

Figure 21-8.

SPI - Slave with DPRAM operation - Third part

In SPI slave mode, the control logic will sample the incoming signal of the HSSCK pin. To

ensure correct sampling of the clock signal, the frequency of the HSSPI clock should never

exceed fSCKmax (fSCKmax=24 Mbits/s). When the HSSPI is enabled, the data direction of the

HSMOSI, HSMISO, HSSCK, and HSSS pins is overridden according to Table 21-1

Table 21-1.

SPI Pin Overrides

Direction, Master SPI

Direction, Slave SPI

MOSI

Output

Input

MISO

Input

Output

SCK

Output

Input

NSS

Output

Input

BTD?

Write 16 in HSSPICNT

Read nb_data in HSSPICNT

Copy nb_data into RAM using

HSSPIDMA.

Read received data directly into RAM

Set bit HSSPICR.STTO

YES

then TIMEOUT

LABEL

"RECEIVE DATA UK"

Clear BTD (HSSPIIR)

Set bit HSSPICR.STTO

Wait BTD or TIMEOUT

Write 16 in HSSPICNT

End of reception.

Next loop

Copy 16 into RAM using HSSPIDMA.

Read received data directly into RAM

Clear TIMEOUT

(HSSPIIR)

Disable DMA

(Clear HSSPICFG.DPRAM)

Enable DMA

(Set HSSPICFG.DPRAM)

Wait DMA ready

(HSSPISR.DPRAMRDY)

AT90SCR100 데이터시트(PDF) 285 Page - ATMEL Corporation

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