전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

EM351-RTR 데이터시트(PDF) 132 Page - List of Unclassifed Manufacturers

부품명 EM351-RTR
상세설명  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  240 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  ETC2 [List of Unclassifed Manufacturers]
홈페이지  
Logo ETC2 - List of Unclassifed Manufacturers

EM351-RTR 데이터시트(HTML) 132 Page - List of Unclassifed Manufacturers

Back Button EM351-RTR Datasheet HTML 128Page - List of Unclassifed Manufacturers EM351-RTR Datasheet HTML 129Page - List of Unclassifed Manufacturers EM351-RTR Datasheet HTML 130Page - List of Unclassifed Manufacturers EM351-RTR Datasheet HTML 131Page - List of Unclassifed Manufacturers EM351-RTR Datasheet HTML 132Page - List of Unclassifed Manufacturers EM351-RTR Datasheet HTML 133Page - List of Unclassifed Manufacturers EM351-RTR Datasheet HTML 134Page - List of Unclassifed Manufacturers EM351-RTR Datasheet HTML 135Page - List of Unclassifed Manufacturers EM351-RTR Datasheet HTML 136Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 132 / 240 page
background image
EM351 / EM357
Figure 9-16. Control Circuit in External Clock Mode 2
9.3.4
Capture/Compare Channels
Each capture/compare channel is built around a capture/compare register including a shadow register, an
input stage for capture with digital filter, multiplexing and prescaler, and an output stage with comparator
and output control.
Figure 9-17 gives an overview of the input stage of one capture/compare channel. The input stage samples the
corresponding TIy input to generate a filtered signal (TIyF). Then an edge detector with polarity selection
generates a signal (TIyFPy) which can be used either as trigger input by the slave mode controller or as the
capture command. It is prescaled before the capture register (ICyPS).
Figure 9-17. Capture/Compare Channel (Example: Channel 1 Input Stage)
The output stage generates an intermediate reference signal, OCyREF, which is only used internally. OCyREF is
always active high, but it may be inverted to create the output signal, OCy, that controls a GPIO output.
Figure 9-18 shows the basic elements of a capture/compare channel.
9-12
120-035X-000D
Preliminary



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com