EM351-RTR datasheet(149/240 Pages) ETC2

149 / 240 page

EM351 / EM357

Figure 9-36. Triggering Timer 1 and 2 with Timer 1 TI1 Input

9.3.15 Timer Signal Descriptions

Table 9-4. Timer Signal Descriptions

Signal

Internal/

External

Description

CK_INT

Internal

Internal clock source: connects to EM35x peripheral clock (PCLK) in internal clock mode.

CK_PSC

Internal

Input to the clock prescaler.

ETR

Internal

External trigger input (used in external timer mode 2): a clock selected by

TIM_EXTRIGSEL in TIMx_OR.

ETRF

Internal

External trigger: ETRP after filtering.

ETRP

Internal

External trigger: ETR after polarity selection, edge detection and prescaling.

ICy

External Input capture or clock: TIy after filtering and edge detection.

ICyPS

Internal

Input capture signal after filtering, edge detection and prescaling: input to the capture

ITR0

Internal

Internal trigger input: connected to the other timer’s output, TRGO.

OCy

External Output compare: TIMxCy when used as an output. Same as OCyREF but includes possible

polarity inversion.

OCyREF

Internal

Output compare reference: always active high, but may be inverted to produce OCy.

PCLK

External Peripheral clock connects to CK_INT and used to clock input filtering. Its frequency is

12 MHz if using the 24 MHz crystal oscillator and 6 MHz if using the 12 MHz RC oscillator.

TIy

Internal

Timer input: TIMxCy when used as a timer input.

TIyFPy

Internal

Timer input after filtering and polarity selection.

TIMxCy

Internal

Timer channel at a GPIO pin: can be a capture input (ICy) or a compare output (OCy).

TIMxCLK External Clock input (if selected) to the external trigger signal (ETR).

TIMxMSK External Clock mask (if enabled) AND’ed with the other timer’s TIMxCLK signal.

TRGI

Internal

Trigger input for slave mode controller.

9-29

120-035X-000D

Preliminary

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