EM351-RTR datasheet(145/240 Pages) ETC2

145 / 240 page

EM351 / EM357

A rising edge on TI1 enables the counter and sets the INT_TIMTIF flag. The counter then counts on ETR rising

edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the

resynchronization circuit on ETRP input.

Figure 9-30. Control circuit in External Clock Mode 2 + Trigger Mode

9.3.14 Timer Synchronization

The two timers can be linked together internally for timer synchronization or chaining. A timer configured in

master mode can reset, start, stop or clock the counter of the other timer configured in slave mode.

Figure 9-31 presents an overview of the trigger selection and the master mode selection blocks.

9.3.14.1

Using One Timer as Prescaler for the Other Timer

For example, to configure Timer 1 to act as a prescaler for Timer 2:

Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each UEV. Writing

TIM_MMS = 010 in the TIM1_CR2 register causes a rising edge to be output on TRGO each time a UEV is

generated.

To connect the TRGO output of Timer 1 to Timer 2, configure Timer 2 in slave mode using ITR0 as an

internal trigger. Write TIM_TS = 100 in the TIM2_SMCR register.

Put the slave mode controller in external clock mode 1: Write TIM_SMS = 111 in the TIM2_SMCR register.

This causes Timer 2 to be clocked by the rising edge of the periodic Timer 1 trigger signal, which

corresponds to the Timer 1 counter overflow.

Finally, enable both timers: Set their respective TIM_CEN bits in the TIMx_CR1 register.

Note:

If OCy is selected on Timer 1 as trigger output (TIM_MMS = 1xx), its rising edge is used to clock the

counter of Timer 2.

Figure 9-31. Master/Slave Timer Example

9-25

120-035X-000D

Preliminary

EM351-RTR 데이터시트(PDF) 145 Page - List of Unclassifed Manufacturers