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EM351-RTR 데이터시트(PDF) 156 Page - List of Unclassifed Manufacturers

부품명 EM351-RTR
상세설명  High-Performance, Integrated ZigBee/802.15.4 System-on-Chip
PDF  240 Pages
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제조업체  ETC2 [List of Unclassifed Manufacturers]
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Logo ETC2 - List of Unclassifed Manufacturers

EM351-RTR 데이터시트(HTML) 156 Page - List of Unclassifed Manufacturers

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EM351 / EM357
TIMx_EGR
TIM1_EGR
Timer 1 Event Generation Register
Address: 0x4000E014 Reset: 0x0
TIM2_EGR
Timer 2 Event Generation Register
Address: 0x4000F014 Reset: 0x0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
TIM_TG
0
TIM_CC4G
TIM_CC3G
TIM_CC2G
TIM_CC1G
TIM_UG
Bitname
Bitfield
Access
Description
TIM_TG
[6]
W
Trigger Generation.
0: Does nothing.
1: Sets the TIM_TIF flag in the INT_TIMxFLAG register.
TIM_CC4G
[4]
W
Capture/Compare 4 Generation.
0: Does nothing.
1: If CC4 configured as output channel:
The TIM_CC4IF flag is set.
If CC4 configured as input channel:
The TIM_CC4IF flag is set.
The INT_TIMMISSCC4IF flag is set if the TIM_CC4IF flag was already high.
The current value of the counter is captured in TMRx_CCR4 register.
TIM_CC3G
[3]
W
Capture/Compare 3 Generation.
0: Does nothing.
1: If CC3 configured as output channel:
The TIM_CC3IF flag is set.
If CC3 configured as input channel:
The TIM_CC3IF flag is set.
The INT_TIMMISSCC3IF flag is set if the TIM_CC3IF flag was already high.
The current value of the counter is captured in TMRx_CCR3 register.
TIM_CC2G
[2]
W
Capture/Compare 2 Generation.
0: Does nothing.
1: If CC2 configured as output channel:
The TIM_CC2IF flag is set.
If CC2 configured as input channel:
The TIM_CC2IF flag is set.
The INT_TIMMISSCC2IF flag is set if the TIM_CC2IF flag was already high.
The current value of the counter is captured in TMRx_CCR2 register.
TIM_CC1G
[1]
W
Capture/Compare 1 Generation.
0: Does nothing.
1: If CC1 configured as output channel:
The TIM_CC1IF flag is set.
If CC1 configured as input channel:
The TIM_CC1IF flag is set.
The INT_TIMMISSCC1IF flag is set if the TIM_CC1IF flag was already high.
The current value of the counter is captured in TMRx_CCR1 register.
TIM_UG
[0]
W
Update Generation.
0: Does nothing.
1: Re-initializes the counter and generates an update of the registers. This also clears the
prescaler counter but the prescaler ratio is not affected. The counter is cleared if center-
aligned mode is selected or if TIM_DIR=0 (up-counting), otherwise it takes the auto-reload
value (TMR1_ARR) if TIM_DIR=1 (down-counting).
9-36
120-035X-000D
Preliminary



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