EM351-RTR datasheet(158/240 Pages) ETC2

158 / 240 page

EM351 / EM357

9-38

120-035X-000D

Preliminary

Bitname

Bitfield

Access

Description

TIM_OC2FE

[10]

Output Compare 2 Fast Enable. (Applies only if TIM_CC2S = 0.)

This bit speeds the effect of an event on the trigger in input on the OC2 output.

0: OC2 behaves normally depending on the counter and TIM_CCR2 values even when the

trigger is ON. The minimum delay to activate OC2 when an edge occurs on the trigger

input is 5 clock cycles.

1: An active edge on the trigger input acts like a compare match on the OC2 output. OC2

is set to the compare level independently from the result of the comparison. Delay to

sample the trigger input and to activate OC2 output is reduced to 3 clock cycles.

TIM_OC2FE acts only if the channel is configured in PWM 1 or PWM 2 mode.

TIM_IC2F

[15:12]

Input Capture 1 Filter. (Applies only if TIM_CC2S > 0.)

This defines the frequency used to sample the TI2 input, Fsampling, and the length of the

digital filter applied to TI2. The digital filter requires N consecutive samples in the same

state before being output.

0000: Fsampling=PCLK, no filtering.

0001: Fsampling=PCLK, N=2.

0010: Fsampling=PCLK, N=4.

0011: Fsampling=PCLK, N=8.

0100: Fsampling=PCLK/2, N=6.

0101: Fsampling=PCLK/2, N=8.

0110: Fsampling=PCLK/4, N=6.

0111: Fsampling=PCLK/4, N=8.

1000: Fsampling=PCLK/8, N=6.

1001: Fsampling=PCLK/8, N=8.

1010: Fsampling=PCLK/16, N=5.

1011: Fsampling=PCLK/16, N=6.

1100: Fsampling=PCLK/16, N=8.

1101: Fsampling=PCLK/32, N=5.

1110: Fsampling=PCLK/32, N=6.

1111: Fsampling=PCLK/32, N=8.

Note: PCLK is 12 MHz when using the 24 MHz crystal oscillator, and 6 MHz using the 12 MHz

RC oscillator.

TIM_IC2PSC

[11:10]

Input Capture 1 Prescaler. (Applies only if TIM_CC2S > 0.)

00: No prescaling, capture each time an edge is detected on the capture input.

01: Capture once every 2 events.

10: Capture once every 4 events.

11: Capture once every 6 events.

TIM_CC2S

[9:8]

Capture / Compare 1 Selection.

This configures the channel as an output or an input. If an input, it selects the input

source.

00: Channel is an output.

01: Channel is an input and is mapped to TI2.

10: Channel is an input and is mapped to TI1.

11: Channel is an input and is mapped to TRGI. This mode requires an internal trigger

input selected by the TIM_TS bit in the TIMx_SMCR register.

Note: TIM_CC2S may be written only when the channel is off (TIM_CC2E = 0 in the

TIMx_CCER register).

TIM_OC1M

[6:4]

Output Compare 1 Mode. (Applies only if TIM_CC1S = 0.)

See TIM_OC2M description above.

TIM_OC1BE

Output Compare 1 Buffer Enable. (Applies only if TIM_CC1S = 0.)

See TIM_OC2BE description above.

TIM_OC1FE

[2]

Output Compare 1 Fast Enable. (Applies only if TIM_CC1S = 0.)

See TIM_OC2FE description above.

TIM_IC1F

[7:4]

Input Capture 1 Filter. (Applies only if TIM_CC1S > 0.)

See TIM_IC2F description above.

TIM_IC1PSC

[3:2]

Input Capture 1 Prescaler. (Applies only if TIM_CC1S > 0.)

See TIM_IC2PSC description above.

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