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MSP430F5529 데이터시트(PDF) 64 Page - Texas Instruments |
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MSP430F5529 데이터시트(HTML) 64 Page - Texas Instruments |
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64 / 115 page ![]() MSP430F551x MSP430F552x SLAS590D – OCTOBER 2009 – REVISED APRIL 2010 www.ti.com Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal: SMCLK, ACLK 1.8 V/ fTA Timer_A input clock frequency External: TACLK 25 MHz 3.0 V Duty cycle = 50% ± 10% All capture inputs. 1.8 V/ tTA,cap Timer_A capture timing Minimum pulse width required for 20 ns 3.0 V capture. Timer_B over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal: SMCLK, ACLK 1.8 V/ fTB Timer_B input clock frequency External: TBCLK 25 MHz 3.0 V Duty cycle = 50% ± 10% All capture inputs. 1.8 V/ tTB,cap Timer_B capture timing Minimum pulse width required for 20 ns 3.0 V capture. USCI (UART Mode) - recommended operating conditions PARAMETER CONDITIONS VCC MIN TYP MAX UNIT Internal: SMCLK, ACLK fUSCI USCI input clock frequency External: UCLK fSYSTEM MHz Duty cycle = 50% ± 10% BITCLK clock frequency fBITCLK 1 MHz (equals baud rate in MBaud) USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 2.2 V 50 600 tt UART receive deglitch time(1) ns 3 V 50 600 (1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized their width should exceed the maximum specification of the deglitch time. 64 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated |
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