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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MSP430F5529 데이터시트(PDF) 19 Page - Texas Instruments |
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MSP430F5529 데이터시트(HTML) 19 Page - Texas Instruments |
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19 / 115 page  MSP430F551x MSP430F552x www.ti.com SLAS590D – OCTOBER 2009 – REVISED APRIL 2010 Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. Table 3. Interrupt Sources, Flags, and Vectors SYSTEM WORD INTERRUPT SOURCE INTERRUPT FLAG PRIORITY INTERRUPT ADDRESS System Reset Power-Up External Reset WDTIFG, KEYV (SYSRSTIV)(1) (2) Reset 0FFFEh 63, highest Watchdog Timeout, Password Violation Flash Memory Password Violation System NMI SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG, PMM VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62 Vacant Memory Access JMBOUTIFG (SYSSNIV)(1) JTAG Mailbox User NMI NMI NMIIFG, OFIFG, ACCVIFG, BUSIFG (Non)maskable 0FFFAh 61 Oscillator Fault (SYSUNIV)(1) (2) Flash Memory Access Violation Comp_B Comparator B interrupt flags (CBIV)(1) (3) Maskable 0FFF8h 60 TB0 TB0CCR0 CCIFG0 (3) Maskable 0FFF6h 59 TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6, TB0 Maskable 0FFF4h 58 TB0IFG (TB0IV)(1) (3) Watchdog Timer_A Interval Timer WDTIFG Maskable 0FFF2h 57 Mode USCI_A0 Receive/Transmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (3) Maskable 0FFF0h 56 USCI_B0 Receive/Transmit UCB0RXIFG, UCB0TXIFG (UCAB0IV)(1) (3) Maskable 0FFEEh 55 ADC12_A ADC12IFG0 to ADC12IFG15 (ADC12IV)(1) (3) (4) Maskable 0FFECh 54 TA0 TA0CCR0 CCIFG0(3) Maskable 0FFEAh 53 TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4, TA0 Maskable 0FFE8h 52 TA0IFG (TA0IV)(1) (3) USB_UBM USB interrupts (USBIV)(1) (3) Maskable 0FFE6h 51 DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) (3) Maskable 0FFE4h 50 TA1 TA1CCR0 CCIFG0(3) Maskable 0FFE2h 49 TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2, TA1 Maskable 0FFE0h 48 TA1IFG (TA1IV)(1) (3) I/O Port P1 P1IFG.0 to P1IFG.7 (P1IV)(1) (3) Maskable 0FFDEh 47 USCI_A1 Receive/Transmit UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (3) Maskable 0FFDCh 46 USCI_B1 Receive/Transmit UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (3) Maskable 0FFDAh 45 TA2 TA2CCR0 CCIFG0(3) Maskable 0FFD8h 44 TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2, TA2 Maskable 0FFD6h 43 TA2IFG (TA2IV)(1) (3) I/O Port P2 P2IFG.0 to P2IFG.7 (P2IV)(1) (3) Maskable 0FFD4h 42 RTCRDYIFG, RTCTEVIFG, RTCAIFG, RTC_A Maskable 0FFD2h 41 RT0PSIFG, RT1PSIFG (RTCIV)(1) (3) 0FFD0h 40 Reserved Reserved(5) ⋮ ⋮ 0FF80h 0, lowest (1) Multiple source flags (2) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it. (3) Interrupt flags are located in the module. (4) Only on devices with ADC, otherwise reserved. (5) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To maintain compatibility with other devices, it is recommended to reserve these locations. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 19 |
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