6402 datasheet(87/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

Clocking

8.9

Additional Clock Modes

8.9.1

Transparent Mode Clocking

In transparent mode, all input signals are registered in the core clock domain and all

outputs are driven from the output of registers clocked by core clock. In order to

achieve determinism on a tester in this mode, the feedback clock for the PLL is taken

from the end of the core clock tree. This makes all timing relative to the input reference

clock.

8.10

PLL Requirements

8.10.1

Jitter

The FBD link clocks are produced by a PLL that multiplies the SCLK frequency. See the

High Speed Differential Point-to-Point Link at 1.5 V for Fully Buffered DIMM

Specification and the Circuit Architecture Specifications for the DDR, FBD and PLL

custom I/Osfor more details.

8.10.2

PLL Bandwidth Requirements

The PLL -3dB loop bandwidth shall be between fREFCLK/18 and fREFCLK/6 with a 3dB

maximum peaking.

See the High Speed Differential Point-to-Point Link at 1.5 V for Fully Buffered DIMM

Specification and the Circuit Architecture Specifications for the DDR, FBD and PLL

custom I/Osfor more details.

8.10.3

External Reference

The PLL uses an external reference clock - described previously.

See the High Speed Differential Point-to-Point Link at 1.5 V for Fully Buffered DIMM

Specificationand the Circuit Architecture Specifications for the DDR, FBD and PLL

custom I/Os for more details.

SCL

SMBus clock

CKE[1:0]{A,B}

DDR clock enables

CLK[3:0]

DDR clocks

CLK[3:0]

DDR clocks (Complements)

DQS[17:0]

DDR data/check-bit strobes

DQS[17:0]

DDR data/check-bit strobes (Complements)

Table 8-3.

Clock Pins (Sheet 2 of 2)

Pin Name

Pin Description

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