6402 datasheet(42/250 Pages) INTEL

42 / 250 page

Electrical, Power, and Thermal

Intel® 6400/6402 Advanced Memory Buffer Datasheet

Idd_Active_

Active Power, data pass

through

L0 state.

50% DRAM BW to downstream

DIMM, 67% read, 33% write.

Primary and Secondary

channels enabled

CKE high. Command and

address lines stable.

DRAM clock active.

@1.5 V

2.9

3.2

3.3

3.7

@1.8 V

0.9

@3.3 V

Idd_Active_2 Total Power

5.5

6.1

Idd_Training

(for AMB

spec, Not in

SPD)

Training

Primary and Secondary

channels enabled.

100% toggle on all channel

lanes

DRAMs idle. 0 BW.

CKE high, Command and

address lines stable.

DRAM clock active.

@1.5 V

3.5

4.0

@1.8 V

0.9

@3.3 V

Idd_Training Total Power

Idd_IBIST

(for AMB

spec, Not in

SPD)

IBIST

Over all IBIST modes

DRAM Idle (0 BW)

Primary channel Enabled

Secondary channel Enabled

CKE high. Command and

Address lines stable

DRAM clock active

@1.5 V

3.8

4.5

@1.8 V

0.9

@3.3 V

Idd_IBIST Total Power

Idd_MemBI

(for AMB

spec, Not in

SPD)

MemBIST

Over all MemBIST modes

>50% DRAM BW (as dictated

by the AMB)

Primary channel Enabled

Secondary channel Enabled

CKE high. Command and

Address lines stable

DRAM clock active

@1.5 V

3.3

3.8

@1.8 V

2.4

@3.3 V

Idd_MemBIST Total Power

Table 4-4.

Power Values for x4 DIMMs (Sheet 2 of 3)

533 MHz

667 MHz

Symbol

Conditions

Power

Supply

Thermal

Design

Max

Current

Thermal

Design

Max

Current

Units

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