6402 datasheet(9/250 Pages) INTEL

9 / 250 page

Intel® 6400/6402 Advanced Memory Buffer Datasheet

10-2 Mapping of FBD Pins in Transparent Mode........................................................... 101

10-3 Mapping of Burst Position Bits to Error Capture.................................................... 106

10-4 Selection of 8 bit Data Paths When ENDOUT is Set............................................... 107

10-5 Transparent Mode FB-DIMM Interface Signaling Specifications............................... 107

11-1 MemBIST Feature Summary ............................................................................. 112

11-2 Memory Address Definition, BL=4...................................................................... 114

11-3 Memory Address Definition, BL=8...................................................................... 115

11-4 MemBIST Addressing Behavior.......................................................................... 116

11-5 Dynamic Address Inversion, XZY Address Sequencing and Range Addressing .......... 122

11-6 Example of Circular Data Shifting ...................................................................... 125

11-7 Example of LFSR Random Data ......................................................................... 126

11-8 Address Log to Bank, Row and Column Bit Correspondence................................... 129

11-9 Failure Data Bit Location Accumulator to MBDATA Bit Correspondence.................... 129

11-10 Failure to Logging Register Correspondence ........................................................ 130

11-11 Refresh Programming ...................................................................................... 132

12-1 655-Ball FBGA 0.8 mm Pitch - Left Side.............................................................. 144

12-2 655-Ball FBGA 0.8 mm Pitch - Right Side............................................................ 145

12-3 Advanced Memory Buffer Signals By Ball Number ................................................ 145

13-1 Signal Naming Conventions .............................................................................. 155

13-2 Buffer Signal Types ......................................................................................... 156

13-3 Pin Description................................................................................................ 156

13-4 Pin Count ....................................................................................................... 158

14-1 Access to “Non-existent” Register Bits................................................................ 159

14-2 Register Attributes Definitions........................................................................... 160

14-3 Function Mapping Legend ................................................................................. 161

14-4 Function 0: PCI Standard Header Identification Registers...................................... 162

14-5 Function 1: FBD Link Registers.......................................................................... 163

14-6 Function 2: Implementation Specific FBD Registers .............................................. 164

14-7 Function 3: DDR and Miscellaneous Registers ..................................................... 165

14-8 Function 4: Implementation Specific DDR Initialization and Calibration Registers ..... 166

14-9 Function 5: DFX Registers ................................................................................ 167

14-10 Function 6: Bring-up and Debug Registers .......................................................... 168

14-11 MBDATA Failure Address Register Correspondence to DRAM Address ...................... 195

14-12 BL4 Column and Chunk Correspondence to DRAM Address.................................... 195

14-13 BL8 Column and Chunk Correspondence to DRAM Address.................................... 196

14-14 Functional Characteristics of DCALADDR............................................................. 205

14-15 Functional Characteristics of DCALDATA for Calibration Algorithms ......................... 206

14-16 Functional Characteristics of DCALDATA for HVM Algorithms ................................. 208

14-17 Bit Locations for SB Match and Mask .................................................................. 224

15-1 Raw Cards A, B, and C ..................................................................................... 243

15-2 Raw Cards D, E, H, and J.................................................................................. 244

15-3 Category ByteJ ............................................................................................... 245

6402 데이터시트(PDF) 9 Page - Intel Corporation

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