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6402 데이터시트(PDF) 31 Page - Intel Corporation |
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6402 데이터시트(HTML) 31 Page - Intel Corporation |
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31 / 250 page ![]() Intel® 6400/6402 Advanced Memory Buffer Datasheet 31 DDR Interface 3.7 S3 State Background Description S3 is a platform power down state where DRAM memory contents are preserved while the rest of the platform powers down. This state is described more formally in the Advanced Configuration and Power Interface Specification. It is much like the Standby mode on mobile computers. Functionally, the requirement for an AMB is that after a sequence in which: • AMBS3 Recovery state is stored by the host, • DRAMs are put into Self-Refresh, • RESET# is asserted, • Vcc (1.5 V), Vtt (0.9 V) and VddSPD(3.3 V) are powered down, The contents of memory on the DIMM are preserved until S3 Recovery. Recovery requires that the memory on the DIMM be restored without losing data integrity. The recovery sequence is much the same as an initial power on with the exceptions of: • Vdd is already powered on • DDR interface state is restored from stored register values (since no calibration which might compromise memory content is allowed) To minimize DIMM current, VCC should be powered up during VTT transitions. The AMB determines that it is in the S3 mode by checking that VDD (1.8 V) is powered up and that VCC (1.5 V) is powered off. When in S3 the AMB drives all command/address outputs (including CKE, ODT, and CLK) to a low. This keeps the DRAM in auto-refresh and helps prevent DRAM data corruption. When coming out of the S3 mode, if the system brings VTT (0.9 V) up before VCC the AMB will drive low into the VTT pull-up circuitry. This causes significant current (approximately two times average but still normal) to flow from VTT into the AMB until VCC is powered up and the AMB comes out of S3. Figure 3-1. Nominal Turnaround Time Timing Diagram DQS DQ Preamble A Preamble B Data A-0 Data A-2 Data A-3 Data A-1 Data B-0 Data B-1 Data B-2 Data B-3 Clock DQS DQ Preamble R (read) Preamble W (write) Data R-0 Data R-2 Data R-3 Data R-1 Data W-0 Data W-1 Data W-2 Data W-3 Clock Postamble A Postamble R DQS DQ Preamble R (read) Preamble W (write) Data R-0 Data R-2 Data R-3 Data R-1 Data W-0 Data W-1 Data W-2 Data W-3 Clock Postamble R Postamble W Read to Read turnaround (nominal) Read to Write turnaround (nominal) Write to Read turnaround (nominal) |
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