6402 datasheet(32/250 Pages) INTEL

32 / 250 page

DDR Interface

Intel® 6400/6402 Advanced Memory Buffer Datasheet

3.7.1

S3 Recovery Configuration Registers

The following CSRs should be stored in non-volatile memory before entering S3 mode

and restored before normal DRAM transactions begin.

•DRC

•MTR

•DSREFTC

•DAREFTC

•DDR2ODTC

•CMD2DATANXT

• S3RESTORE[15:0]

• PERSBYTE[13:0] - SPD Personality Bytes

3.8

DDR Calibration

The following sections describe these DDR calibration and initialization features:

• DRAM initialization and (E)MRS command CSR’s and FSM

• DQS failure CSR

• DQS receive enable calibration

• DQS calibration

3.8.1

DRAM Initialization and (E)MRS FSM

The AMB provides a set of CSR’s and an FSM that allow BIOS to manage DRAM power

up initialization and set DRAM mode register bits. All commands needed for DRAM

initialization can be generated, including precharge, refresh, mode register set (MRS),

and extended mode register set EMRS commands. A self-refresh command can also be

generated, although this is not required for initialization. The initialization/(E)MRS FSM

only controls the issuing of single commands, and does not automatically initialize the

DRAM. It is the responsibility of software to control the command sequence to correctly

initialize the DRAM.

The set of CSR’s include the DCALCSR and DCALADDR registers. The fields of these

CSR’s are described in detail in the configuration register chapter.

The DCALCSR is used to select the command to be issued, which ranks to select, start

the FSM that issues the command, and provide completion status.

The DCALADDR sets the bank and address issued to the DRAM, and therefore defines

the type of (E)MRS to be issued, including limited OCD commands. The DCALADDR can

also be used to configure a precharge command as a “precharge all” command.

DCALADDR[31:16] defines the DDR address bus during these commands, and

DCALADDR[2:0] defines the ddr bank address bus.

The FSM that controls this function can have as few as three states: idle, issue

command, and clear start bit. When the DCALCSR.START bit is set, and the

DCALCSR.OPCODE bits select one of the command options, the FSM transitions from

idle to the “issue command” state. After the command is issued, the FSM clears the

DCALCSR.START bit and returns to the idle state. A more elaborate FSM may also be

implemented. Firmware is required to control the minimum command spacing to meet

all DRAM timing requirements. After setting the start bit, firmware should poll the

6402 데이터시트(PDF) 32 Page - Intel Corporation

6402 데이터시트(HTML) 32 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL