6402 datasheet(46/250 Pages) INTEL

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Electrical, Power, and Thermal

Intel® 6400/6402 Advanced Memory Buffer Datasheet

4.4

DDR2 Electrical Output Timing Specifications

4.4.1

Description of DQ/DQS Alignment

The DQS output rising edge aligns with the CLK output rising edge and the DQS output

falling edge aligns with the CLK output falling edge. The DQ outputs are 1/4 cycle offset

from the DQS outputs.

DQ/DQS inputs are edge aligned and will be skewed by internal receiver DLL. Inputs

are terminated on-die by a resistive circuit during reads only.

4.4.2

Description of ADD/CMD/CNTL Outputs

ADD/CMD/CNTL outputs can be adjusted relative to CLK (see Table 4-8.) to improve

setup or hold times. The value of this delay is fixed at boot time. These outputs are

either aligned with CLK falling or with a certain timing offset before CLK falling. The

amount of offset is implementation specific (for example, can be a constant timing

offset, or a known ratio of the DRAM clock period).

4.4.3

Test Load Specification

DDR2 timings are specified for a 25 Ohm test load terminated to Vdd/2, measured at

the Advance Memory Buffer component package pins.

4.4.4

tDVA and tDVB Parameter Description

The timing parameters tDVA and tDVB indicate the time the DQ is valid after or before

DQS. tDVA is used to indicate the time that Data is Valid After. tDVA is used for DQ/

DQS write hold calculations (tDH). tDVB is used to indicate the time that Data is Valid

Before. tDVB is used for DQ/DQS write setup calculations (tDS).

4.4.5

tjit and tjitHP Parameter Description

The parameter tjit is the full period jitter, and tjitHP is the half-period jitter.

Figure 4-2. tDVA and tDVB Timing Diagram

DQS/DQS

From AMB

DQ From

AMB

tDVA

tDVB

6402 데이터시트(PDF) 46 Page - Intel Corporation