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PIC24F16KA102 데이터시트(PDF) 29 Page - Microchip Technology

부품명 PIC24F16KA102
상세설명  Flash Programming Specifications
PDF  48 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC24F16KA102 데이터시트(HTML) 29 Page - Microchip Technology

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PIC24FXXKAXXX
© 2008 Microchip Technology Inc.
Advance Information
DS39919A-page 29
DSWDTPS<3:0>
FDS<3:0>
Deep Sleep Watchdog Timer Postscale Select bits
The DSWDT prescaler is 32; this creates an approximate base time unit of
1 ms.
1111
= 1:2,147,483,648 (25.7 days)
1110
= 1:536,870,912 (6.4 days)
1101
= 1:134,217,728 (38.5 hours)
1100
= 1:33,554,432 (9.6 hours)
1011
= 1:8,388,608 (2.4 hours)
1010
= 1:2,097,152 (36 minutes)
1001
= 1:524,288 (9 minutes)
1000
= 1:131,072 (135 seconds)
0111
= 1:32,768 (34 seconds)
0110
= 1:8,192 (8.5 seconds)
0101
= 1:2,048 (2.1 seconds)
0100
= 1:512 (528 ms)
0011
= 1:128 (132 ms)
0010
= 1:32 (33 ms)
0001
= 1:8 (8.3 ms)
0000
= 1:2 (2.1 ms)
DSZPBOR
FDS<6>
Deep Sleep Zero-Power BOR Enable bit
1
= Zero-Power BOR enabled in Deep Sleep
0
= Zero-Power BOR disabled in Deep Sleep (does not affect operation in non
Deep Sleep modes)
FCKSM<1:0>
FOSC<7:6>
Clock Switching and Monitor Selection Configuration bits
1x
= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01
= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00
= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
FNOSC<2:0>
FOSCSEL<2:0> Oscillator Selection bits
000
= Fast RC Oscillator (FRC)
001
= Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
010
= Primary Oscillator (XT, HS, EC)
011
= Primary Oscillator with PLL module (HS+PLL, EC+PLL)
100
= Secondary Oscillator (SOSC)
101
= Low-Power RC Oscillator (LPRC)
110
= Reserved; do not use
111
= Fast RC Oscillator with divide-by-N (FRCDIV)
FWDTEN
FWDT<7>
Watchdog Timer Enable bit
1
= WDT enabled
0
= WDT disabled (control is placed on the SWDTEN bit)
GSS0
FGS<1>
General Segment Code Flash Code Protection bit
1
= No protection
0
= Standard security enabled
GWRP
FGS<0>
General Segment Code Flash Write Protection bit
1
= General segment may be written
0
= General segment is write-protected
ICS<1:0>
FICD<1:0>
ICD Pin Placement Select bit
11
= ICD EMUC/EMUD pins are shared with PGEC1/PGED1
10
= ICD EMUC/EMUD pins are shared with PGEC2/PGED2
01
= ICD EMUC/EMUD pins are shared with PGEC3/PGED3
00
= Reserved; do not use
TABLE 4-2:
PIC24FXXKAXXX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
Note 1:
Applies only to the 28-pin device.
2:
The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user
from accidentally locking out the device from low-voltage test entry.



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