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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIC24F16KA102 데이터시트(PDF) 45 Page - Microchip Technology |
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PIC24F16KA102 데이터시트(HTML) 45 Page - Microchip Technology |
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45 / 48 page  PIC24FXXKAXXX © 2008 Microchip Technology Inc. Advance Information DS39919A-page 45 7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS TABLE 7-1: STANDARD OPERATING CONDITIONS Standard Operating Conditions Operating Temperature: 0 °C to +70°C and programming: +25°C is recommended. Param No. Symbol Characteristic Min Max Units Conditions D111 VDD Supply Voltage During Programming VDDCORE 3.60 V Normal programming D112 IPP Programming Current on MCLR —50 μA— D113 IDDP Supply Current During Programming — 2 mA — D031 VIL Input Low Voltage VSS 0.2 VDD V— D041 VIH Input High Voltage 0.8 VDD VDD V— D042 VIHH Programing Voltage on VPP VDD +1.5 9 V — D080 VOL Output Low Voltage — 0.4 V IOL = 8.5 mA @ 3.6V D090 VOH Output High Voltage 1.4 — V IOH = -3.0 mA @ 3.6V D012 CIO Capacitive Loading on I/O pin (PGDx) — 50 pF To meet AC specifications P1 TPGC Serial Clock (PGCx) Period 125 — ns — P1A TPGCL Serial Clock (PGCx) Low Time 50 — ns — P1B TPGCH Serial Clock (PGCx) High Time 50 — ns — P2 TSET1 Input Data Setup Time to Serial Clock ↑ 15 — ns — P3 THLD1 Input Data Hold Time from PGCx ↑ 15 — ns — P4 TDLY1 Delay Between 4-Bit Command and Command Operand 40 — ns — P4A TDLY1A Delay Between 4-Bit Command Operand and the Next 4-Bit Command 40 — ns — P5 TDLY2 Delay Between Last PGCx ↓ of Command Byte and First PGCx ↑ of Read of Data Word 20 — ns — P6 TSET2VDD ↑ Setup Time to MCLR ↑ 100 — ns — P7 THLD2 Input Data Hold Time from MCLR ↑ VPP↓ (from VIHH to VIH) 25 — ms — P8 TDLY3 Delay Between Last PGCx ↓ of Command Byte and PGDx ↑ by Programming Executive 12 — μs— P9 TDLY4 Programming Executive Command Processing Time 40 — μs— P10 TDLY6 PGCx Low Time After Programming 400 — ns — P11 TDLY7 Chip Erase Time 5 — ms — P12 TDLY10 Page (4 rows) Erase Time 5 — ms — P13 TDLY9 Row Programming Time 2 — ms — P14 TR MCLR Rise Time to Enter ICSP™ mode — 1.0 μs— P15 TVALID Data Out Valid from PGCx ↑ 10 — ns — P16 TDLY10 Delay Between Last PGCx ↓ and MCLR ↓ 0— s — P17 THLD3MCLR ↓ to VDD ↓ —100 ns — P18 TKEY1 Delay Between First MCLR ↓ and First PGCx ↑ for Key Sequence on PGDx 40 — ns — P19 TKEY2 Delay Between Last PGCx ↓ for Key Sequence on PGDx and Second MCLR ↑ 1— ms — |
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