XPC8260ZUIFBC datasheet(23/50 Pages) FREESCALE

23 / 50 page

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0

Freescale Semiconductor

Clock Configuration Modes

To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the

MODCK[1–3] pins are sampled while HRESET is asserted. Table 13 lists the eight basic configuration

modes. Table 14 lists the other modes that are available by using the configuration pin (RSTCONF) and

driving four bits from hardware configuration word on the data bus.

Note that the MPC8265 and the MPC8266 have two additional clocking modes—PCI agent and PCI host.

Refer to Section 3.2, “PCI Mode” on page 26 for information.

NOTE

Clock configurations change only after POR is asserted.

3.1

Local Bus Mode

Table 13 describes default clock modes for the MPC826xA.

Table 14 describes all possible clock configurations when using the hard reset configuration sequence.

Note that basic modes are shown in boldface type. The frequencies listed are for the purpose of illustration

only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed

the frequency rating of the user’s device.

Table 13. Clock Default Modes

MODCK[1–3]

Input Clock

Frequency

CPM Multiplication

Factor

CPM

Frequency

Core Multiplication

Factor

Core

Frequency

000

33 MHz

100 MHz

133 MHz

001

33 MHz

100 MHz

166 MHz

010

33 MHz

133 MHz

011

33 MHz

133 MHz

166 MHz

100

66 MHz

133 MHz

2.5

166 MHz

101

66 MHz

133 MHz

200 MHz

110

66 MHz

2.5

166 MHz

2.5

166 MHz

111

66 MHz

2.5

166 MHz

200 MHz

Table 14. Clock Configuration Modes1

MODCK_H–MODCK[1–3]

Input Clock

Frequency2,3

CPM Multiplication

Factor2

CPM

Frequency2

Core Multiplication

Factor2

Core

Frequency2

0001_000

33 MHz

66 MHz

133 MHz

0001_001

33 MHz

66 MHz

166 MHz

0001_010

33 MHz

66 MHz

200 MHz

0001_011

33 MHz

66 MHz

233 MHz

0001_100

33 MHz

66 MHz

266 MHz

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