APA600 datasheet(71/178 Pages) MICROSEMI

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ProASICPLUS Flash Family FPGAs

v5.9

2-61

Synchronous Write and Read to the Same Location

Note: * New data is read if WCLKS

↑ occurs before setup time. The data stored is read if WCLKS ↑ occurs after hold time. The plot shows

the normal operation status.

Figure 2-34 • Synchronous Write and Read to the Same Location

Table 2-58 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial

TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883

Symbol txxx

Description

Min.

Max.

Units

Notes

CCYC

Cycle time

7.5

CMH

Clock high phase

3.0

CML

Clock low phase

3.0

WCLKRCLKS

WCLKS

↑ to RCLKS ↑ setup time

– 0.1

WCLKRCLKH

WCLKS

↑ to RCLKS ↑ hold time

7.0

OCH

Old DO valid from RCLKS

↑

3.0

OCA/OCH displayed for

Access Timed Output

OCA

New DO valid from RCLKS

↑

7.5

Notes:

1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output.

2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write

clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS

and RCLKS driven by the same design signal.

3. If WCLKS changes after the hold time, the data will be read.

4. A setup or hold time violation will result in unknown output data.

RCLKS

WCLKS

WCLKRCLKH

New Data*

Last Cycle Data

WCLKRCLKS

OCH

CCYC

CMH

CML

OCA

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