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AN4228 데이터시트(PDF) 13 Page - STMicroelectronics |
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AN4228 데이터시트(HTML) 13 Page - STMicroelectronics |
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13 / 90 page ![]() DocID024110 Rev 5 13/90 AN4228 Peripheral migration 89 3.2 System architecture The main system consists of: Five masters: – Cortex-M4 core I-bus – Cortex-M4 core D-bus – Cortex-M4 core S-bus – GP-DMA1 and GP-DMA2 (general-purpose DMAs) Seven or six slaves in STM32F30xx microcontrollers depending on the CCM RAM and FMC availability in the product: – Internal Flash memory on the DCode and ICode – CCM SRAM on STM32F303xB/C/D/E and STM32F303x6/x8 – Internal SRAM – AHB to APBx (APB1 or APB2), which connect all the APB peripherals – AHB dedicated to GPIO ports – ADCs –FMC Five slaves in STM32F37xx microcontrollers: – Internal Flash memory on the DCode – Internal Flash memory on the ICode – 2 Kbyte internal SRAM memory – AHB to APBx (APB1 or APB2) connecting all the APB peripherals – AHB dedicated to GPIO ports. These are interconnected using a multilayer AHB bus architecture as shown in Figure 1 and Figure 2. |
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