IMX7SCEC datasheet(113/152 Pages) NXP

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Boot mode configuration

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

113

Boot mode configuration

This section provides information on Boot mode configuration pins allocation and boot devices interfaces

allocation.

5.1

Boot mode configuration pins

Table 89 provides boot options, functionality, fuse values, and associated pins. Several input pins are also

sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.

The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an

unblown fuse). For detailed Boot mode options configured by the Boot mode pins, see the “System Boot,

Fusemap, and eFuse” chapter in the i.MX 7Solo Application Processor Reference Manual (IMX7SRM).

Power Down Current2

IPD3

—

3.0

300

μΑ

Signal to Noise and Distortion Ratio

SNDR

—

1 Normal operation current consumption includes only the current from the ADC core. It does not include static current from the

power pads.

2 Power-down current includes only the current from the ADC core. It does not include static current from the power pads.

3 IOP and IPD are measurable only on the ADC core's test chips. Because AVDD10 is shared with internal logic power, IOP

and IPD in the test plan only measure current consumption @ AVDD18, VREF.

Table 89. Fuses and associated pins used for boot

Direction

at Reset

eFuse

name

State during reset

(POR_B

asserted)

State after reset

(POR_B

deasserted)

Details

BOOT_MODE0

Input

N/A

Hi-Z

Boot mode selection

BOOT_MODE1

Input

N/A

Hi-Z

Boot mode selection

Table 88. AC Electrical characteristics(continued)

Specification

Symbol

Min

Typ

Max

Unit

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