IMX7SCEC datasheet(114/152 Pages) NXP

114 / 152 page

Boot mode configuration

i.MX 7Solo Family of Applications Processors Datasheet, Rev. 5, 07/2017

NXP Semiconductors

114

5.2

Boot device interface allocation

Table 90 lists the interfaces that can be used by the boot process in accordance with the specific Boot

mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,

which are configured during boot when appropriate.

LCD1_DATA00

Input

BT_CFG[0]

100K Pull Down

Keeper

Boot options, pin value overrides fuse

settings for BT_FUSE_SEL=’0’. Signal

configuration as fuse override input at

power up.

These are special I/O lines that control the

boot configuration during product

development. In production, the boot

configuration can be controlled by fuses.

LCD1_DATA01

Input

BT_CFG[1]

100K Pull Down

Keeper

LCD1_DATA02

Input

BT_CFG[2]

100K Pull Down

Keeper

LCD1_DATA03

Input

BT_CFG[3]

100K Pull Down

Keeper

LCD1_DATA04

Input

BT_CFG[4]

100K Pull Down

Keeper

LCD1_DATA05

Input

BT_CFG[5]

100K Pull Down

Keeper

LCD1_DATA06

Input

BT_CFG[6]

100K Pull Down

Keeper

LCD1_DATA07

Input

BT_CFG[7]

100K Pull Down

Keeper

LCD1_DATA08

Input

BT_CFG[8]

100K Pull Down

Keeper

LCD1_DATA09

Input

BT_CFG[9]

100K Pull Down

Keeper

LCD1_DATA10

Input

BT_CFG[10]

100K Pull Down

Keeper

LCD1_DATA11

Input

BT_CFG[11]

100K Pull Down

Keeper

LCD1_DATA12

Input

BT_CFG[12]

100K Pull Down

Keeper

LCD1_DATA13

Input

BT_CFG[13]

100K Pull Down

Keeper

LCD1_DATA14

Input

BT_CFG[14]

100K Pull Down

Keeper

LCD1_DATA15

Input

BT_CFG[15]

100K Pull Down

Keeper

LCD1_DATA16

Input

BT_CFG[16]

100K Pull Down

Keeper

LCD1_DATA17

Input

BT_CFG[17]

100K Pull Down

Keeper

LCD1_DATA18

Input

BT_CFG[18]

100K Pull Down

Keeper

LCD1_DATA19

Input

BT_CFG[19]

100K Pull Down

Keeper

Table 90. Interface allocation during boot

Interface

IP Instance

Allocated Pads During Boot

Comment

QSPI

EPDC_D0, EPDC_D1, EPDC_D2, EPDC_D3,

EPDC_D4, EPDC_D5, EPDC_D6, EPDC_D7,

EPDC_D8, EPDC_D9, EPDC_D10, EPDC_D11,

EPDC_D12, EPDC_D13, EPDC_D14, EPDC_D15

SPI

ECSPI-1

ECSPI1_SCLK, ECSPI1_MOSI, ECSPI1_MISO,

ECSPI1_SS0, UART1_RXD, UART1_TXD,

UART2_RXD

The chip-select pin used depends

on the fuse "CS select (SPI only)"

Table 89. Fuses and associated pins used for boot(continued)

Direction

at Reset

eFuse

name

State during reset

(POR_B

asserted)

State after reset

(POR_B

deasserted)

Details

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