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AR8327-AL1A-R 데이터시트(PDF) 20 Page - List of Unclassifed Manufacturers

부품명 AR8327-AL1A-R
상세설명  Seven-port Gigabit Ethernet Switch
PDF  394 Pages
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제조업체  ETC2 [List of Unclassifed Manufacturers]
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AR8327-AL1A-R 데이터시트(HTML) 20 Page - List of Unclassifed Manufacturers

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20 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch
Atheros Communications, Inc.
20 • June 2011
COMPANY CONFIDENTIAL
NOTE: For a 2-layer PCB design, we strongly recommend the use of external power — 1.1V for AVDD and
DVDD. This will reduce thermal effects.
NOTE: For a four-layer PCB design, we strongly recommend the use of a reserve external power supply for
AVDD and DVDD when using the internal switch regulator.
The following table shows the interface summary relative to the AR8327’s different modes.
VDD33
A6, A10, B15, A27, A33,
A36, A42
p
Analog 3.3V power input
VDD25_REG
A9
AO
The 2.5V power output
VDD25_IO
B41, B46, A63, B73
p
The 2.5V power source for IO pad
AVDDVCO_O
A12
OA
Analog 1.25V power output for VCO
AVDDVCO_I
A34
P
Analog 1.25V power input for VCO and connected to
pin A12
FILCAP[0:7]
A3, B12, B18, B19, A30,
B31, A39
I
Connect to an external capacitor 0.1uF for power
stable.
AVDD25
A11
Analog 2.5V input. Connect this pin to pin A9 and
add 0.1uF capacitor to this pin.
Table 1-2.
Interface Summary for MAC0, MAC6 or PHY4
PAD name
Pin
I/O
GMII PHY mode
(MAC0)
2RGMII
(MAC0+ MAC6)
2RGMII (MAC0+
PHY4)
GTXCLK_0
A73
I/O
txclk_0 (O)
txclk_0 (I)
txclk_0 (I)
TXEN_0
A72
I
txen_0
txen_0
txen_0
TXD0_0
B63
I
txd0_
txd0_0
txd0_0
TXD1_0
A74
I
txd1_0
txd1_0
txd1_0
TXD2_0
B64
I
txd2_0
txd2_0
txd2_0
TXD3_0
A75
I
txd3_0
txd3_0
txd3_0
RXCLK_0
A65
O
rxclk_0 (O)
rxclk_0 (O)
rxclk_0 (O)
RXDV_0
A64
O
rxdv_0
rxdv_0
rxdv_0
RXD0_0
A68
O
rxd0_0
rxd0_0
rxd0_0
RXD1_0
A69
O
rxd1_0
rxd1_0
rxd1_0
RXD2_0
A70
O
rxd2_0
rxd2_0
rxd2_0
RXD3_0
B60
O
rxd3_0
rxd3_0
rxd3_0
GTXCLK_1
B51
I
gtxclk_0 (I)
txclk_6 (I)
txclk_phy4 (I)
TXEN_1
A58
I
—
txen_6
txctl_phy4
TXD0_1
A59
I
txd4_0
txd0_6
txd0_phy4
TXD1_1
B52
I
txd5_0
txd1_6
txd1_phy4
Symbol
Pin
Type
Description



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