AR8327-AL1A-R datasheet(60/394 Pages) ETC2

60 / 394 page

60 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch

Atheros Communications, Inc.

60 • June 2011

COMPANY CONFIDENTIAL

3.2.3

PORT5 PAD MODE CTRL

Address 0x0008

HW RST

R/W

SGMII_CLK125M_RX_SEL

Configure the receive clock phase for MAC

interface and must be set when using

SerDes or SGMII module.

0 = rising edge

1 = falling edge

R/W

SGMII_CLK125M_TX_SEL

Configure the transmit clock phase for

SerDes interface

0 = rising edge

1 = falling edge

R/O

Reserved

R/O

Reserved

R/O

Reserved

R/W

Mac0_phy_gmii_en

1'b1 mac0 connected to cpu through GMII

interface, phy mode

R/W

Mac0_phy_gmii_txclk_sel

1'b1 select invert clock input for port0

phymode, GMII interface txclk

R/W

Mac0_phy_gmii_rxclk_sel

1'b1 select invert clock output for port0

phymode, GMII interface rxclk

R/W

Mac0_phy_mii_pipe_rxclk_se

1'b1 select clock edge for rxpipe,default is

invert

R/W

Mac0_phy_mii_en

1'b1 mac0 connected to cpu through MII

interface, phy mode

R/W

Mac0_phy_mii_txclk_sel

1'b1 select invert clock output for port0

phymode ,MII interface txclk

R/W

Mac0_phy_mii_rxclk_sel

1'b1 select invert clock output for port0

phymode ,MII interface rxclk

R/W

Mac0_sgmii_en

R/W

Mac0_mac_gmii_en

1'b1 mac0 connected to cpu through GMII

interface, mac mode

R/W

Mac0_mac_gmii_txclk_sel

1'b1 select invert clock output for port0

macmode, GMII interface txclk

R/W

Mac0_mac_gmii_rxclk_sel

1'b1 select invert clock input for port0

macmode, GMII interface rxclk

3R/O

RESERVED

R/W

Mac0_mac_mii_en

1'b1 mac0 connected to cpu through MII

interface, mac mode

R/W

Mac0_mac_mii_txclk_sel

1'b1 select invert clock input for port0

macmode, MII interface txclk

R/W

Mac0_mac_mii_rxclk_sel

1'b1 select invert clock input for port0

macmode, MII interface rxclk

Table 3-5.

PORT0 PAD MODE CTRL Register

Bit

R/W

Inital

Value

Mnemonic

Description

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