AR8327-AL1A-R datasheet(71/394 Pages) ETC2

71 / 394 page

Atheros Communications, Inc.

AR8327/AR8327N Seven-port Gigabit Ethernet

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Table 3-17 summarizes the BIST_CTRL Register.

3.2.15

BIST_RECOVER

Address 0x0044

HW RST

Table 3-17.

Bist Control Register

Bit

R/W

Inital

Value

Mnemonic

Description

R/W

BIST_BUSY

This bit should be written to 1'b1 to

begin bist test and should be cleared to

1'b0 by hardware after test done.

1'b1: bist test

1'b0:bist done or idle

R/O

BIST_WITH_ONE_ERR

1'b1: bist test one error in data memory

and can be recoverd.

R/O

BIST_PASS

All memory is OK, or only one error in

data memory.

28:24

R/O

RESERVED

R/W

BIST_CRITICAL

R/W

BIST_PTN_EN_2

1'b1: enable pattern 2 for bist test

R/W

BIST_PTN_EN_1

1'b1: enable pattern 1 for bist test

R/W

BIST_PTN_EN_0

1'b1: enable pattern 0 for bist test

19:12

R/O

RESERVED

R/O

OFFLOAD_BIST_DONE

R/O

OFFLOAD_BIST_ERR

R/O

QM_BIST_DONE

R/O

QM_BIST_ERR

R/O

LOOKUP_BIST_DONE

R/O

LOOKUP_BIST_ERR

5R/O

MIB_BIST_DONE

R/O

MIB_BIST_ERR

3R/O

ACL_BIST_DONE

R/O

ACL_BIST_ERR

1R/O

ARB_BIST_DONE

R/O

ARB_BIST_ERR

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